This paper describes the development of SiC MOSFET model for high temperature applications. The temperature dependence of the threshold voltage and mobility of SiC MOSFET is quite different from that of silicon MOSFET. We developed the empirical temperature model of threshold voltage and mobility of SiC MOSFET and implemented into HSPICE. Using this model the MOSFET Id-Vds characteristics as a function of temperature are simillated. Also the SiC CMOS operational amplifieris designed using this model and the temperature dependence of the frequency response, transfer characteristics and slew rate as a function of temperature are analyzed.

In oriental medicine, it is possible to classify each person into eight kinds of constitutions based on the eight constitutional medicine theory. We developed a piezoelectric 3-channel tactile sensor using PVDF (polyvinylidene fluoride) film for pulse detection of the radial artery. High frequency buffer (impulse buffer), amplifier, 60 Hz noise notch filter and low pass filter were integrated on three sheets of PCB board. The pulses of the radial artery at three points were checked using our system. Each constitution of the eight ones has different combinations of pulses.

InP/InGaAs Heterojunction phototransistors(HPT's) with an optically transparent ITO emitter electrode were fabricated and characterized. At the same time, heterojuntion transistors(HBT's) having the same device layout were fabricated. By comparison with InP/InGaAs HBT's, the do characteristics of InP/InGaAs HPT's showed the similar electrical charateristics of HBT's. the model parameters of the device were extracted and compared.

In this paper, film bulk acoustic resonator(FBAR) with an air-gap is fabricated by removing ZnO sacrificial layer and its characteristics as a various dimension of ZnO sacrificial and piezoelectric layer is evaluated. The center frequency of the FBAR device with the ZnO film is about 1.9 GHz. Because of mass-loading effect, a dimension of sacrificial layer and piezoelectrc layer affect frequency response such as center frequency, insertion loss, band separation, attenuation and so on.

We studied aluminum cluster deposition using molecular dynamics simulation. We investigated the variations of the cluster momentum and the impulse force during collisions, and found that the close-packed cluster impact has some of properties of the single particle collision and the linear chain collisions. We also simulated the series of energetic cluster deposition with energy Per atom. When energy Per atom in cluster has some eV rather than very low, the intermixing occurred easily in growth film and we can obtain a good film without subsequent annealing process.

In this paper, we have investigated the effects of gas flow rate, rf power, process pressure and Ar addition on reactive ion etching of InP, InGaAs and InAlAs using Sic14 and Cl$_2$ gases. The etch rates were measured by using a surface profiler. The etched profiles, sidewall roughness, and surface morphology were observed by scanning electron microscopy and by atomic force microscopy. The selective etching of InGaAs to InP and InAlAs was studied by varying the etching parameters. It was found that Cl$_2$ gas is more efficient for the selective etching of InGaAs to InAlAs than SiCl$_4$ gas. The etch selectivity of InGaAs to InAlAs is strongly dependent on the rf power and the process pressure.

In this paper, the thermal oxidation behaviors and the electrical characteristics of the thermal oxide grown on SiC are discussed. For these studies the oxide layers with various thickness were on SiC in wet $O_2$ or dry $O_2$ at l15$0^{\circ}C$ and the MOS capacitors using the 350$\AA$ gate oxide grown in wet $O_2$ were fabricated and electrically characterized. It was found from the experimental results that the oxidation rate of SiC with the Si-face and with the carbon-face were about 10% and 50% of oxidation rate of Si. The C-V measurement results of the SiC oxide showed abnormal hysterisis properties which had ever been not observed for the Si oxide. And the hysterisis behavior was seen more significant when initial bias voltage was more negative or more positive. The hysterisis property of the SiC oxide was believed to be due the substantial amount of the deep level traps to exist at the interface between the oxide and the SiC substrate. The leakage of the SiC oxide was found to be one order larger than the Si oxide, but the breakdown strength was almost equal to that of the Si oxide.

In this paper, we have studied the characteristics of wet etching using citric acid based wet etchant. We have used the citric acid / hydrogen peroxide solution, citric acid / hydrogen peroxide / D.I. water solution. From our experimental result, a volumetric 1：3 ratio of citric acid and hydrogen peroxide and 1 ： 3 ： 1 ratio of citric acid, hydrogen peroxide, and D.I. water is shown to be a better wet etchant of PHEMT's system.

The semiconductor's design rule becomes more stringent, hence the silicon-dioxide etching technique is important issue. In this work we compared the etching characteristics of different three types of Plasma source, Normal ICP, magnetized ICP and E-IC $P^{TM}$. The E-IC $P^{TM}$ source shows higher etch rate at lower pressure and this is advantageous for the fine pattern process. The etching characteristics were varied with external magnetic field frequency at I-lCP and this is examined with Nanospe $c^{TM}$ and SEM. We designed Langmuir probe system for time resolved diagnosis. ion density of E-ICP is varying periodically with the applied external magnetic field frequencyquency

본 논문은 액정 Driver IC에 사용되a는 내부 기준 clock 발생 및 Voltage Converter에 boosting을 하기 위한 clock을 제공하는 Oscillator 설계 및 구현 하였다 LCD Driver IC에서 발생되는 Oscillator clock 은 고속의 clock신호는 필요로 하지 않으나 LCD display에 관련된 frame 주파수에 직접적인 영향을 주므로 중심 주파수 결정 및 duty비에 따른 주파수 제어가 매우 중요하다. 본 논문에서는 가변 duty를 적용하는 LCD system에 적용할 수 있는 가변 duty oscillator를 소개한다. Process는 0.35um, 12V공정을 사용하였다.

An programmable current-mode folding and interpolation analog to digital converter (ADC) with programmable interpolator is proposed in this paper. A programmable interpolator is employed not only to vary the resolution of data converter, but also to decrease a power dissipation within the ADC. Because of varying the number of interpolation circuits, resolution is vary from 6 to 10bit. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The experimental result shows the power dissipation from 26 to 87mW with a power supply of 3.3V.

The electrochemical characteristics of Alalloy thin film with low impurity concentrations AIZr deposited by using do magnetron co-sputtering deposition are investigated for the applications as gate bus line in the TFT-LCD panel. AlZr thin films were deposited various atomic percent of Zr. For increasing Zr atomic percent the hillock density was decreased and the resistivity was increased. The deposited thin films show the decrease of resistivity and the increase of grain size after the RTA at 300 $^{\circ}C$for 20 min.. Moreover, the resistivity of AIZr does not show appreciable grain size dependence after RTA. It is concluded that the decrease of resistivity after RTA is due to the increase of grain size. The annealed AIZr(at.0.9%) is found to be hillock free. The electrode potentials of AIZr were less than ITO's (-1.4V) and the etching rate of AIZr(at.0.9%) was 3.8587ng/sec. in KOH(10%) solution. Caculation results reveal that the AIZr(at.0.9%) thin film can be applicable to gate line of 25" UXGA class TFT-LCD panels and can not be applicable to data line.line.

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

A readout circuit for Dual band IR detector was proposed and designed. Designed circuit provide to detector a stable diode bias and high injection efficiency using Buffered Direct Injection (BDI) input circuit. Then, amplifier in the unit cell is operated when cell is selected in order to minimize the power consumption. We could confirm through the simulation that designed circuit integrate and output simultaneously the signal generating from the dual band IR detector.

In this paper a binary image encryption technique and decryption system based on a joint transform correlator (JTC) are Proposed. In this method, a Fourier transform of the encrypted image is used as the encrypted data and a Fourier transform of the random phase is used as the key code. The original binary image can be reconstructed on a square law device, such as a CCD camera after the joint input is inverse Fourier transformed. The proposed encryption technique does not suffer from strong auto-correlation terms appearing in the output plane. Based on computer simulations, the proposed encryption technique and decoding system were demonstrated as adequate for optical security applications.

We have studied the fabrication tolerance of a fused vertical coupler switch with switching operation induced section and extinction ratio enhanced section to obtain more than 30dB extinction ratio for both cross and bar states with less than 500 ${\mu}{\textrm}{m}$ device length for various thicknesses of inner cladding layer.

Optical visual cryptography was proposed by conjunction of the optical theory with the cryptography. However, it had some difficulties. The problems occurred in the process of transferring data processing system from visual to optics. Therefore, it is appropriate to approach these problems in terms of optics. The results show that the optical visual cryptography system has both the effectiveness and reliability as well as real-time implementation property.

In this paper, we proposed a personal identification method using binay image encryption technique and decryption system in JTC structure. Logo which represents the group symbol was encrypted with personal fingerprint and JTC structure decrypts this logo. The logo can not decrypted by other unused fingerprint even if the encrypted image was lost or stolen. So this method can give more safe personal identification.

In recent years, the design of CMOS VCO at ever-higher frequencies has gained interest. This paper proposes an arithmetic functionality VCO circuit based on a differential ring oscillator for operating in high frequency. The proposed VCO architecture with half adder is able to produce two times higher frequency with my delay cell than conventional VCO produce double oscillation frequency and power dissipation is 14.59mW.

This paper suggests an improved switch architecture for the rechargeable battery protection IC. In the existing protection IC, charging and discharging switches composed of the CMOS transistor and the diode are external components. It is difficult to integrate the switches in a CMOS process due to the large chip-size overhead and inevitable parasitic effects. In this paper, we propose a new switch architecture of the MOSFET's 'diode connection' method. The performance and chip-size overhead are proved to be adequate for the fully integrated protection IC.

In this paper, a simple low-power CMOS current reference circuit is proposed. The reference circuit includes parasitic pnp BJTs and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a base-to-emitter voltage. The designed circuit has been simulated using a 0.25${\mu}{\textrm}{m}$ n-well CMOS process parameters. The simulation results show that the reference current is 34.96$mutextrm{A}$$\pm$0.04$mutextrm{A}$ in the temperature range of -2$0^{\circ}C$ to 12$0^{\circ}C$ The reference current varies less than 0.6% when the power supply voltage changes from 2.5V to 3.5V For $V_{DD=5V}$ and T=3$0^{\circ}C$ the power consumption is 520㎼ during normal operation but reduces to 0.l㎻ during power-down mode.

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

A 3-way VLIW multimedia signal processor capable of efficient repeated operations as well as both load/store and type transformations for various data types is presented. It is composed of a 32-bit execution unit that can execute two instructions in parallel, an independent load/store unit and a control unit. The processor is implemented with 0.6${\mu}{\textrm}{m}$ gate array and the results are discussed.

In this paper, we have analyzed algorithm about physical layer, data link layer and MAC layer of out-of-band specified in the DVS 178 and designed architecture of Out-of-band processor. Out-of-band processor extracts session key information from EMM packet to descramble MPEG-2 TS packet scrambled. Also, analyze EAS Packet including emergency alert information to provide emergency communications such as national emergency. In this paper, we have implemented prototype board for out-of-band processor.

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

In this paper, I present a MPEG4 decoding system modeling in SystemC, a new C/C++ based system simulation approach, In the modeling, MPEG4 decoding behavior is modeled and verified. And I partitions the MPEG4 decoding system into several hardware components which will be implemented at low level hardware design flow and I model a synchronized hardware block communication through data ports.

In this paper we present a new hierarchical layout object extraction algorithm, which is based on rectangles rather than edges. The original layout data is modeled as instances connected by wires. Each polygon shape is divided into a set of rectangles and the instances and wires are extracted and recognized from those rectangles together with their connection and size information. We have applied the algorithm to actual layouts. Experiments on several standard cell library demonstrate the effectiveness of the algorithm.

This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.

This paper proposed resource allocation algorithm for the minimum switching activity of functional unit in high level synthesis process as like DSP which is circuit to give many functional unit. The resource allocation method after scheduling use the power function calculating average hamming distance and switching activity of the between two input. First of all, the switching activity is calculated by the input value after calculating the average hamming distance between operation. In this paper, the proposed method though high If level simulation find switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity find the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and max control step. And it is the reduction effect from 6% to 8%.

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

This paper presents an efficient method to estimate the maximum SSN (simultaneous switching noise) for ground interconnection networks in CMOS systems using Taylor's series and analyzes the truncation error that has occurred in Taylor's series approximation. We assume that the curve form of noise voltage on ground interconnection networks is linear and derive a polynomial expression to estimate the maximum value of SSN using $\alpha$-power MOS model. The maximum relative error due to the truncation is shown to be under 1.87% through simulations when we approximate the noise expression in the 3rd-order polynomial.

A new package design method to reduce resonance effect due to an IC package is represented. Frequency-variant circuit model of the power/ground plane was developed to accurately reflect the resonance. The circuit model is benchmarked with a full wave simulation, thereby verifying its accuracy. Then it was shown that the proposed technique can efficiently reduce the resonance due to the IC package.

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

In this paper, polycrystalline silicon thin film transistor using by Solid Phase Crystallization(SPC) were fabricated, and these devices were measured and analyzed the electrical output and transfer characteristics along to DC voltage stress. The transfer characteristics of polycrystalline silicon thin film transistor depended on drain and gate voltages. Threshold voltage is high with long channel length and narrow channel width. And output characteristics of polycrystalline silicon thin film transistor flowed abruptly much higher drain current. The devices induced electrical stress are decreased drain current. At last, field effect mobility is the faster as channel length is high and channel width is narrow.

In this paper, a 1.5V 2㎓ low-power peak detector is presented. Analyzing the designed peak detector circuit which is composed with two NMOSs, two diodes, and two capacitors, the detection characteristic relationships are derived. The simulation results with SPICE for 2㎓ pulse signals and sinusoidal signals on the 1.5V supply voltages show the good detection characteristics for input signal levels of 50㎷~500㎷, and show very small power dissipation of 0.332㎽.

This paper describes a 12-bit high speed pipeline CMOS A/D converter. The A/D converter simulated the 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. The results show DNL and INL of $\pm$0.5LSB and $\pm$1.0LSB, conversion rate of 100Msamples/s, and power dissipation of 500㎽ with a power supply of 3.3V

소자 내부의 전위와 전자 및 정공 의사 페르미 준위에 따른 반송자의 정확한 농도를 얻기 위해 Fermi-Dirac통계를 구현하는 방법을 제시하였다. 또한 Fermi-Dirac통계를 고려하여 반도체 방정식을 이산화하는 방법을 제안한다. 제안된 방법을 검증하기 위해 전력 바이폴라 접합 트랜지스터를 제작하였으며 모의 실험 결과 컬렉터-에미터 전압 대 컬렉터 전류는 현재 업계에서 상용화된 소자의 실측치와 비교하여 최대 15%이내의 상대오차를 보였다.

정상상태에서 소자 내부의 격자온도 분포를 해석할 수 있는 시뮬레이터를 제작하였다. Slotboom 변수를 사용하여 열흐름 방정식을 이산화하였다. 또한 격자온도 분포를 고려한 초기 해의 설정 방법을 제안하였다. 제안된 방법의 타당성을 검증하기 위하여 N/sup ＋ P 정합 다이오드에 대해 모의실험을 수행하여 MEDICI의 결과와 비교하였다 순방향 전압-전류 특성은 MEDICI의 결과와 비교하여 7% 이내의 최대 상대오차를 보였고 전위 분포와 온도 분포는 각각 2%, 2% 이내의 최대 상대오차를 보였다. BANDIS에서는 수렴을 위해 평균 3.7회 이하의 행렬 연산이 필요하였으며, MEDICI에서는 평균 5.1회 이하의 행렬 연산이 필요하였다.

고 전계하에서 수직 및 수평 전계의 영향을 고려할 수 있는 Hewlett-Packard 이동도 모델을 구현하였다. HP 이동도 모델은 BANDIS에 구현되었다. 구현된 HP이동도 모델을 검증하기 위해 N-MOSFET과 P-MOSFET에 대해 모의실험을 수행하여 MEDICI와 비교한 결과, 드레인 전압-드레인 전류는 5% 이내의 최대 상대 오차를 보였고 전위 분포는 5% 이내의 최대 상대오차를 보였다. MEDICI에서는 1회 수렴을 하기위해 평균 4.6회 이하의 행렬 연산이 필요한 반면 BANDIS에서는 평균 4.3회 이하의 행렬 연산이 필요하다.

We have investigated the mechanical deformation of carbon nanotube using TBMD(tight-binding molecular dynamics) simulation. We have studied four carbon nanotubes, armchair (6, 6), (7, 7), (8, 8), and (9, 9) carbon nanotubes whose length were same. As a result of study, we have known that the nanotube's yield force increases with incresing their diameter. It is similar between (6, 6) and (8, 8) CNT's force-strain curves. Also force-strain curve between (7,7) and (9, 9) CNTs are nearly same.

A new EMI estimation technique concerned with a PDP system is presented. A physical circuit model is developed which can fairly well describe the AC-PDP system. Then EMIs are determined by exploiting Hertzian dipole antenna model. The simulation results are experimentally verified with the test panel. The AC PDP system was measured in the frequency range of 30MHz ~ 300MHz in a semi-anechoic chamber, according to CISPR 13 code. Thereby, it is shown that the proposed technique can be usefully employed for EMI reduction.

The quantum effects in the channel of a $\delta$ -doped NMOSFET structures are investigated by solving Schrodinger and Poisson equations self-consistently. According to the scaling of MOSFET structures, electron distributions change by the strong energy quantization. However the presence of a low-doped epitaxial region produces a reduction of the electron effective field for a given charge sheet density and therefore, improves the electron effective mobility. We also focus the quantum-induced threshold voltage shifts, low-field electron effective mobility and gate-to-channel capacitance. The reported results give indications for the fabrication of ultra short MOSFET's.

A coplanar waveguide(CPW) on a dielectric substrate consists of a center strip conductor with semi-infinite ground planes on either side. This type of waveguide offers several advantages over microstrip line. It facilitates easy shunt as well as series mounting of active and passive devices. It eliminates the need for wraparound and via holes, and it has a low radiation loss. These, as well as several other advantages, make CPW ideally suited for microwave integrated circuit applications. However, very little information is available in the literature on models for CPW discontinuities. This lack of sufficient discontinuity models for CPW has limited the application of CPW in microwave circuit design. We presented for the characteristics of coplanar waveguide open end capacitance and series gap capacitance. Measurements by utilizing the resonance method were made and the experimental data confirmed the validity of theories. The relationships between the CPW capacitances and the physical dimensions were studied.

In this study, $Al_2$O$_3$films have been deposited with Atomic Layer Deposition(ALD) for gate insulator for MPTMA and $H_2O$ at low temperature below 40$0^{\circ}C$ . Conventional methods of $Al_2$O$_3$thin film deposition have suffered from the poor step coverage due to reduction of device dimension and increasing contact/via hole aspect ratio. ALD is a self-limiting growth process with controlled surface reaction where the growth rate is only dependent on the number of growth cycle and the lattice parameter of materials. ALD growth process has many advantages including accurate thickness control, large area and large batch capability, good uniformity, and pinholes freeness.

We have studied fabrication processes that form asymmetric $\Gamma$-gate with a 0.1${\mu}{\textrm}{m}$ gate length in MMIC's(Monolithic Microwave Integrated Circuits). Asymmetric $\Gamma$-gate was fabricated using mixture of PMMA and MCB. Thus pseudomorphic high electron mobility transistor (PHEMT's) with 0.1${\mu}{\textrm}{m}$ gate length was fabricated via several steps such as mesa isolation, metalization, recess, passivation. PHEMT's has the -1.75 V of pinch-off voltage (Vp), 63 mA of drain saturation current(Idss and 363.6 mS/mm of maximum transconductance (Gm) in DC characteristics and current gain cut-off frequency of 106 GHz and maximum frequency of oscillation of 160 GHz in RF characteristics.

One of the major reasons for not integrating a VCO on one-chip in a PLL (phase locked loop) system is the large chip-to-chip variation of the VCO (voltage controlled oscillator) center frequency. In this thesis, a simple bias technique is proposed to compensate the process fluctuation. The proposed bias technique is applied to the VCO and it reduces the deviation of the VCO center frequency from 35% to 8 %. With the suggested bias technique, a 400 MHz frequency synthesizer is designed for general purpose. It utilizes a programmable divider for various division ratio. The design methodology provides the possibility of the one-chip solution for a PLL system.

Novel Enhanced Inductively Coupled Plasma is applied to etch $SiO_2$. Effect of $O_2$ or Ar addition to $C_{4}F_{8}$ gas is monitored by Optical Emission Spectroscopy and Quadrupole Mass Spectrometer. It is fund that Ar or $O_2$ dilution to $C_{4}F_{8}$ increases F emission intensity and decreases $CF_2$ intensity. However, the ac frequency to the Helmholtz coil decreases the F intensity and thus increases $CF_2$/F ratio. By adjusting the ac frequency, the optimum etch rate and PR to $SiO_2$ selectivity can be obtained in E-lCP.

LDMOSFET devices operated at low temperature have applications on satellite, space shuttle and low temperature system, etc. In this study, we measured the electrical characteristics of 100v Class LDMOSFET for low temperature application. Measurement data are taken over a wide range of temperatures (100K-300K) and various drift region lengths(6.6${\mu}{\textrm}{m}$, 8.4${\mu}{\textrm}{m}$, 12.6${\mu}{\textrm}{m}$). Maximum transconductance, $g_{m}$ and drain current at low temperatures(~100K) increased over about 260%, 50% respectively, in comparison with the data at room temperature. Breakdown voltage B $V_{ds}$, and specific on- resistance decreased. Besides, ratio $R_{on}$ BV, a figure of merit of the device, decreased with decreasing temperature.

Schottky barrier diodes are fabricated on a intrinsic GaN(4${\mu}{\textrm}{m}$) epitaxial structure grown by rf plasma molecular beam epitaxy (MBE) on sapphire substrates. First, We make Ohmic electrodes (Ti/Al/Ti/Au) by evaporator. Next, we contact RuO$_2$ by dipping in the solution (RuCl$_3$.HClO$_4$), and then we deposit Ni/Au on the surface of RuO$_2$ by evaporator. We study the electrical characteristics of GaN Schottky barrier diodes made by these methods. Measurements are C-V, I-V, SEM, EDX, and XRD for the characteristics of devices. Thickness of RuO$_2$ layer depends on supplied voltage and dipping time. Device of thinner RuO$_2$ layer have a good Schottky characteristics compare with device of thicker RuO$_2$ layer

High quality Taros thin films have been obtained from anodizing. The as-deposited amorphous films have excellent physical and electrical properties: refractive indices ~2.15, dielectric constants ~25, and leakage currents <10$^{-8}$ Ac $m^{-2}$ at 1MV $cm^{-1}$ , 700$\AA$ thickness. We fabricated a MIM element with theses T $a_2$ $O_{5}$ films which had perfect current-voltage symmetry characteristics using a new process technology which was post annealing of whole MIM element instead of conventional annealing conditions (top-electrode metals, annealing conditions) on the capacitor performances were extensively discussed throughout this work.k.

The use of a thin film of indium between the ITO and the $n^{+}$-InP contact layers for InP/InGaAs HPTs was studied without degrading its excellent optical transmittance properties. ITO/$n^{+}$-InP ohmic contact was successfully achieved by the deposition of Indium and thermal annealing. The specific contact resistance of about 6.6$\times$$10^{-4}$$\Omega\textrm{cm}^2$ was measured by use of the transmission line method (TLM). However, as the thermal annealing was just performed to ITO/$n^{+}$-InP contact without the deposition of Indium between ITO and $n^{+}$-InP, it exhibited schottky characteristics. In the applications, the DC characteristics of InP/InGaAs HPTs with ITO emitter contacts was compared with that of InP/InGaAs HBTs with the opaque emitter contacts.

Modified Materka-Kacprzak 대신호 MODFET(modulation-doped field-effect transistor) model을 사용하여 GaN(gallium nitride) MODFET 대신호 모델링을 수행하였다. Dambrine(3)이 제안한 방법에 따라 45㎒에서 40㎒의 주파수 범위에 걸쳐 S-parameter 및 DC특성을 측정하였으며, 측정결과를 토대로 cold FET 방법［4］에 의해 측정된 기생성분들을 de-embedding 함으로써 소신호 파라미터를 추출하였고, 추출된 소신호 파라미터는 함수를 사용하여 측정결과를 재현하는 맞춤함수 모델의 일종인 modified Materka 모델을 사용하여 모델링하였다. 수행된 대신호 모델링을 검증하기 위하여 모델링된 GaN MODFET의 DC 및 S-파라미터, 전력특성을 측정값과 각각 비교해 보았을 때 비교적 일치하고 있음을 보여서 GaN 대신호 모델링을 검증하였으며, modified Materka 모델이 GaN MODFET 대신호 모델링에 유용하게 사용될 수 있음을 보였다.

In this paper, the bonding wire interconnection has been studied from the points of view of modeling and electrical characterization. The bonding wire is measured by TDR(Time Domain Reflectometry) and Network analyzer(1-10㎓). First, one gold bonding wire mounted on 2mm gap substrate measured 3.68nH by TDR and 3.39nH by Network analyzer(6㎓). Two gold bonding wire mounted on 2mm gap substrate measured 3.14nH by TDR and 2.80nH by Network analyzer. This result presented that inductance of bonding wire could be employed as inductors for radio frequency circuit packaging.

We simulated and analyzed the flicker phenomena in the poly-Si TFT-LCD using PSpice for the development of wide-area and high-quality LCD display We define the electric quantity of flicker in the TFT-LCD, which is the ratio of half frame frequency (30Hz) to DC (0 Hz) frequency. We compared two different types of TFTs, excimer laser annealed (ELA) poly-Si TFT and silicide mediated crystallization (SMC) poly-Si TFT, and found that the ELA and SMC TFTs show different flicker characteristics because of their mobility and leakage current. In addition, we showed that the gate voltage should be chosen carefully at the minimum flicker because of the larger leakage current of poly-Si Tn as compared with a-Si TFT

Modified Materka-Kacprzak 대신호 MESFET(Metal Semiconductor Field Effect Transistor) model을 사용하여 4H-SiC MESFET의 대신호 모델링을 수행하였다. Silvaco사의 소자 시뮬레이터인 ATLAS를 사용하여 4H-SiC MESFET 소자 시뮬레이션을 수행하고, 이 절과를 modified Materka 대신호 모델을 사용하여 모델링 하였다. 시뮬레이션 및 모델링 결과는 -8V의 pinch off 전압과 V/sub GS=0V, V/sub DS=25V에서 I/sub DSS=270㎃/㎜, G/sub m=45㎳/㎜를 얻을 수 있었고, 진력 특성 시뮬레이션을 통해 2㎓, V/sub GS=-4V, V/sub DS=25V에서 1()dB의 Gain과 34dBm(1dB compression point)의 출력전력, 7.6W/㎜의 전력밀도, 37%의 PAE(power added efficiency)를 얻을 수 있었다.

We have designed and fabricated ASK modulator MMIC operating at 5.8GHz for OBE used in AGPS (Automatic Gate Passing System). ASK modulator MMIC was designed to apply a sing1e supply voltage of 3V to the drain in order to decrease ACP (Adjacent Channel Power). The measurement result of this chip exhibits on/off characteristic over 30dB. The design parameters are optimized through ADS simulation tool. The layouts and fabrication o( ASK Modulator MMIC were designed and fabricated by using ETRI 0.5${\mu}{\textrm}{m}$ MESFET library. The chip sizes were 1mm $\times$1mm. The performance analysis of the implemented ASK Modulator based on the design parameters is accomplished.

In this paper, we have presented processing technique about wet etching for silicon membrane construction formation. In order to make selective etching of backside silicon wafer, we used Si$_3$N$_4$ layer by PECVD(Plasma Enhanced Chemical Vapor Deposition). We have measured the surface thickness in backside silicon wafer after anisortropic wet etching with KOH:distilled water solutions. Through this experiment, we acquired the etching rate for 1.29${\mu}{\textrm}{m}$/min. The average rough of Si-membrane frontside and backside was 0.26${\mu}{\textrm}{m}$, 0.90${\mu}{\textrm}{m}$, respectively.

At atmosphere photoluminescence(PL) of porous silicon(PSi) decreases and peak wave number of PL is shifted to blue region. When PS is used light detector, the ageing effects are negative phenomena. For controling ageing effects, this paper uses Polymers.

The paper describes the physical design flow of QPSK Demodulator in operating 60MHz. It includes problems and issues of each design flow, verification process for physical layout.

This paper introduces the design of high-speed analog- to-digital converter for high-definition TV, camcorders, portable equipments and implemented in a 0.65${\mu}{\textrm}{m}$ CMOS technology. Key circuits developed for low power and high speed A/D converter are a dynamic comparator that consumes no static power, a source follower buffered op amp that achives wide bandwidth using large input devices. The converter achieves low power dissipation of 40-mW at 3.3-V power supply. Measured performance includes 0.53 LSB of INL and 0.48 LSB of DNL while sampling at 60MHz.

Routing region modeling methods for PCB auto-routing system in Shape based type(non-grid method) used region process type and the shape located in memory as a individual element, and this element consumed small memory due to unique data size. In this paper we design PCB(Printed Circuit Board) auto-routing system using the auction algorithm method that 1) Could be reached by solving the shortest path from single original point to various destination, and 2) Shaped based type without any memory dissipation with the best speed. Also, the auto-routing system developed by Visual C++ in Window environment, and can be used in IBM Pentium computer or in various individual PC system.

In this paper, we design IP of ATM AAL layer for B-ISDN. The designed ATM AAL module supports the function for AAL type 0, AAL type 3/4, AAL type 5. The designed IP provides for automatic CRC-32 and CRC-10 for AAL type and AAL type 3/4. Also our IP inserts and extracts the header and trailer for each type automatically. After HDL description, it is verified by the simulation. The designed U is implemented in Xilinx FPGA. Rx AAL module operates at 35MHz and Rx AAL module operates at 50MHz. The designed IP can be applicable in high-speed ATM SAR(Segmentation and Reassembly) chip.

In this paper we investigate the implementation cost of value prediction methods for high performance micro-processors, and propose a new value prediction microarchitecture with low cost. After simulation, we found that the proposed microarchitecture can decrease the implementation cost by 36% to 50% and with slight performance degradation (less than 5%) .

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

The origin of image-slicking in metal-insulator-metal type thin-film-diode(TFD) LCDs is the asymmetric current-voltage(I-V) characteristic of TFD element. we developed that MIM-LCDs have reduced-image-sticking and perfect symmetry characteristic. One-Time Post-Annealing (OPTA) heat treatment process was introduced to reduce the asymmetry and shift of the I-V characteristics, respectively. OPTA means that the whole layers of lower metal, insulator, and uuper metal are annealed at one time. The treatment temperatures and fabricated process of TFD element were under foot. Also, this low temperature fabricated process allows the application of plastic substrates.

The proposed clock generator lowers the operating frequency in a system core though it keeps data bandwidth high because it has a multiphase clocking architecture. Moreover. it has a dual loop which is comprised of an inner analog phase generation loop and outer digital phase control loop. It has both advantages of DLL's wide operating range and DLL's low jitter The proposed design has been demonstrated in terms of the concept and Hspice simulation. All circuits were designed using a 0.25${\mu}{\textrm}{m}$ CMOS process and simulated with 2.5 V power supply.

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

In this paper a design of cryptographic coprocessor which implements AES Rijndael algorithm is described. To achieve average throughput of 1 round per 5 clocks, subround pipelined scheme is applied. To apply the coprocessor to various applications, three key sizes such as 128, 192, 256 bits are supported. The cryptographic coprocessor is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology and consists of about 36, 000 gates. Its peak performance is about 512 Mbps encryption or decryption rate under 200 Mhz clock frequency and 128-bit key ECB mode(AES-128ECB).

A Novel fully-differential bipolar current-controlled current amplifier(CCCA) for electrically tunable circuit design at current-mode signal processing were designed. The CCCA was consisted of fully-differential subtracter and fully-differential current gain amplifier. The simulation result shows that the CCCA has current input impedance of 0.5 Ω and a good linearity. The CCCA has 3-dB cutoff frequency of 20 MHz for the range over bias current 100$mutextrm{A}$ to 20 ㎃. The power dissipation is 3 mW.

This paper describes an implementation of 4$^{th}$ order single-loop Butterworth noise shaper for a 16-bit $\Delta$$\Sigma$ DAC with the viewpoint of minimum hardware overhead. we adopt simple bit-shifting scheme and ROM selection technique for the multiplication, and propose a new buffer-and-routing method for the ROM circuits. The behavioral level and timing simulations reveal that our proposal is valid for the target specificationrget specificationn

Turbo code shows the great performance near Shannon limit on AWGN channel. Mainly, turbo code has been studied and designed for wireless digital communications. There are recent studies that applies turbo decoder on magnetic recording. Because of the limited capacity of magnetic storages, high rate turbo code is used for magnetic storages. This paper presents some issues on implementing high rate turbo code and structures for designing turbo decoder

The analog multiplier is very useful building block in many circuits such as filter, frequency-shifter, and modulators. In recent year, The main design issue of circuit designer is low-voltage/low-power system design, because of all systems are recommended very integrated system and portable system In this paper, the proposed the four-quadrant analog multiplier is using the bulk-driven techniques. The bulk-driven technique is very useful technique in low-voltage system, compare with gate-driven technique. therefore the proposed analog multiplier is operated in 1V supply voltage. And the proposed analog multiplier is low power dissipation compare with the others. therefor the proposed analog multiplier is convenient in low-voltage/low-power in system.

This paper describes the design of elliptic curve cryptographic (ECC) coprocessor over binary fields for the If card. This coprocessor is implemented by the shift-and-add algorithm for the field multiplication algorithm. And the modified almost inverse algorithm(MAIA) is selected for the inverse multiplication algorithm. These two algorithms is merged to minimize the hardware size. Scalar multiplication is performed by the binary Non Adjacent Format(NAF) method. The ECC we have implemented is defined over the field GF(2$^{163}$), which is a SEC-2 recommendation［7］..

A primitive gas classification system which can classify limited species of gas was designed and simulated. The 'electronic nose' consists of an array of 4 metal oxide gas sensors with different selectivity patterns, signal collecting unit and a signal pattern recognition and decision Part in PLD(programmable logic device) chip. Sensor array consists of four commercial, tin oxide based, semiconductor type gas sensors. BP(back propagation) neutral networks with MLP(Multilayer Perceptron) structure was designed and implemented on CPLD of fifty thousand gate level chip by VHDL language for processing the input signals from 4 gas sensors and qualification of gases in air. The network contained four input units, one hidden layer with 4 neurons and output with 4 regular neurons. The 'electronic nose' system was successfully classified 4 kinds of industrial gases in computer simulation.

In this paper we present the design of a JPEG Encoder using SystemC Methodology Our methodology supports the efficient mapping of C/C++ functional descriptions directly into hardware. The use of C/C++ to model al1 parts of the system provides great flexibility and enables faster simulation compared to existing methodologies. The designer can estimate system performance and verify functional correctness of the designs using commonly available software compilers. A design flow in SystemC begins with an untimed description in C++, using a library of new data types useful for modeling hardware. The description can be compiled and simulated for functional correctness. Then, the design may be refined by adding interface specification and timing information, and again the timed description can be compiled with a standard C++ compiler, simulated, and debugged.

In this paper, Variable width system bus provides a variable data bus width from 8bit to 128bit. This paper has designed variable width system bus controller for microcontroller to connect to peripherals.

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.

This paper describes a VHDL code coverage checker for If design and verification. Applying the verification coverage to IP design is a methodology rapidly gaining popularity. This enables the designers to improve the IP design quality and reduces the time-to-market by providing the Quantitative measure of simulation completeness and test benches. To support this methodology, a VHDL code coverage model was defined and the measurement tool was developed.

This paper proposes a capacitance extraction algorithm based on boundary element method and describes the implemented 2-dimension extractor based on the proposed algorithm. The proposed algorithm uses a generalized conjugate residual iterative algorithm with a hierarchical subdivision. The implemented 2-D extractor computes the capacitances of complicated 2-D geometry of ideal conductors in uniform dielectric and can be efficiently used in the VLSI layout designs due to its user-friendly GUI.

This paper describes the design and implementation results of 40, 32, 24 and 16kbps ADPCM encoder and decoder circuit, based on the protocol CCITT G.726. We verified the ADPCM algorithm using C language and designed the RTL circuit with Verilog HDL. The circuit has been simulated by Verilog-XL, synthesized by Design Compiler and verified using Xilinx FPGA. Since the synthesized circuit includes a small number of gates, it is expected to be used as a core module in the digital voice and image processing SOC.

In this Paper, 3 digit-Serial multilier With 3 digit size of 32 is proposed, which has more advantages than the 193bit serial LFSR architecture. We give a design example for the irreducible trinomials $x^{193}$＋ $x^{15＋1}$. In hardware implementations, it is often desirable to use the irreducible trinomial equations. The proposed multiplier is verified with a VHDL description using an elliptic curve addition. The measured results show that the proposed multiplier is 0.3 times smaller than the bit-serial LFSR multiplier..

본 논문에서는 타원곡선 알고리즘에 기반한 공개키암호시스템 구현을 다룬다. 공개키의 길이는 193비트를 갖고 기약다항식은 p(x)=x/sup 193＋x/sup 15＋1을 사용하였다. 타원곡선은 polynomial basis 로 표현하였으며 SEC 2 파라메터를 기준으로 하였다 암호시스템은 polynomial basis 유한체 연산기로 구성되며 특히, digit-serial 구조로 스마트카드와 같이 제한된 면적에서 구현이 가능하도록 하였다. 시스템의 회로는 VHDL, SYNOPSYS 시뮬레이션 및 회로합성을 이용하여 XILINX FPGA로 회로를 구현하였다. 본 시스템 은 Diffie-Hellman 키교환에 적용하여 동작을 검증하였다.

In this paper, we present a effective low-power technique which can reduce significantly the switching activity in instruction address bus, pipeline and I-cache. Using this method, named Guarded Operation, we has implemented address register. address bus architecture without complex hardware and designed loop buffer without tag. These architectures reduce 67% of switching activity with little overhead and also increase instruction-fetch performance.

As microprocessor and SOC (System On a Chip) performance moves into the GHz speed, the high-speed asynchronous design is becoming challenge due to the disadvantageous power and speed aspects in synchronous designs. The next generation on-chip systems will consist of multiple independently synchronous modules and asynchronous modules for higher performance, so the interface module for data transfer between multiple clocked IPs is designed with Xilinx FPGA and simulated with RISC microprocessor.

This paper proposes an efficient method for 3-dimensional capacitance extraction based on Finite Element Method(FEM). This method expands the conventional FEM by adopting variable division. This method improves the extraction efficiency 2 to 100 times and even the accuracy 1% to 3% when compared to the conventional FEM with equal division. The Proposed method can be used efficiency to extract electrical parameters of on/off-chip interconnects in VLSI systems.

As SOC design methodology becomes popular, processors, the essential core in embedded system are required to be designed fast and supported to customers with expansive behavior description. This paper presents new methodology to meet such goals with designer configurable instruction set simulator for processors. This paper proposes new language called PML(Processor Modeling Language), which is based on microprogramming scheme and is also successful in most behavior of processors. By using this, we can describe scalar processor very efficiently with by-far faster simulation speed in compared with HDL model.

This paper presents a simple method for estimating the maximum crosstalk noise of on-chip grobal wires. For the derivation of the maximum crosstalk expression we have modeled wires using lumped-elements that are composed of R, L and C. We have also used experimental constant to reduce the modeling error. The accuracy of the proposed method is verified by comparing against the HSPICE simulation results under the present process parameters and environmental conditions. The results of the proposed method can be used as an estimator in design-aid tools.

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

This paper presents the design of high-speed virtual output queue(VOQ) management scheme for high performance cell/packet switch, which has a serial cross bar structure. The proposed VOQ management scheme has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the VOQ manager and central arbiter using a new request control method that is based on a high-speed shifter. The designed VOQ manager has been implemented in a field programmable gate array chip with a 77MHz operating frequency, a 900-pin fine ball grid array package, and 16$\times$16 switch size.

This paper has been studied a real-time video frame data processing control that used the linear systolic array for motion estimation. The proposed data control processing provides to the input data into the multiple processor array unit(MPAU) from search area and reference block data. The proposed data control architecture has based on two slice band for input data processing. And it has no required external control logic blocks for input data as like reference block or search area data.

In this paper, we propose new partial product compressor and ENMODL (Enhanced-NORA-MODL) CLA(Carry Look-ahead Adder) for high speed and low power multiplier. To reduce transistor count, area, power we developed two new-approaches. One is small size partial product compressor, the other is dynamic CMOS logic ENMODL CLA. The transistor count of new compressor is reduced by 11% as compared with that of conventional one. The speed of ENMODL CLA is increased by 6.27% as compared with NMODL CLA.

This paper describes the features and development of a RAM compiler that can generate low power, high speed, synchronous CMOS SRAM. The compiled SRAM can be configurable from 64bytes to 16Kbytes in one bank and has 2ns access time typically. Basic cells are developed using 2-poly, 4-metal 0.35um CMOS technology. This SRAM compiler is developed using SKIL $L^{TM}$ language and generates layout and schematic in Cadence environment.