Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of New Partial Product Compressor and ENMODL CLA for High Speed and Low Power Multiplier

고속 저전력 곱셈기를 위한 새로운 부분곱 압축기와 ENMODL CLA의 설계

  • 백한석 (경상대학교 전자공학과) ;
  • 진중호 (경상대학교 전자공학과) ;
  • 송근호 (경상대학교 전자공학과) ;
  • 문성룡 (경상대학교 전자공학과) ;
  • 한석붕 (경상대학교 전자공학과) ;
  • 김강철 (여수대학교 컴퓨터공학과)
  • Published : 2001.06.01
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Abstract

In this paper, we propose new partial product compressor and ENMODL (Enhanced-NORA-MODL) CLA(Carry Look-ahead Adder) for high speed and low power multiplier. To reduce transistor count, area, power we developed two new-approaches. One is small size partial product compressor, the other is dynamic CMOS logic ENMODL CLA. The transistor count of new compressor is reduced by 11% as compared with that of conventional one. The speed of ENMODL CLA is increased by 6.27% as compared with NMODL CLA.

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