Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2001.06b
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- Pages.325-328
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- 2001
VHDL Code Coverage Checker for IP Design and Verification
IP 설계 환경을 위한 VHDL Code Coverage Checker
Abstract
This paper describes a VHDL code coverage checker for If design and verification. Applying the verification coverage to IP design is a methodology rapidly gaining popularity. This enables the designers to improve the IP design quality and reduces the time-to-market by providing the Quantitative measure of simulation completeness and test benches. To support this methodology, a VHDL code coverage model was defined and the measurement tool was developed.
Keywords