Developing of HW/SW Co-Design and Verification Environment for Information-App1iance-On-a-Chip

정보기기온칩을 위한 HW/SW 혼합 설계 및 검증 환경 개발

This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.