In this paper, we have studied optimal FCL(Frequently Called List) table sizes in a grid topology circuit-switched network including wireless subscribers. The FCL table gives the position information of a destination subscriber for a call. When the call is generated in a node, this call is routed by the referenced position information of the destination subscriber in FCL table. In this paper, we have proposed an efficient routing algorithm, mixed FSR(Flood Search Routing) and DAR(Dynamic Adaptive Routing), considering moving wireless subscribers. Also, we have simulated hit ratio and incorrect ratio as performance parameters, consequently proposed the object function composed of table search time, hit ratio, incorrect ratio, FSR time and DAR time, and derived the optimal FCL table size by using it.

This paper presents a CATV SMS (Status Monitoring System) using HDLC (High Level Data Link Contorl) protocol and the system implementation.The system specifications were derived from the analysis of technical status and requirement of the domestic CATV industry. For the interoperability with a global network management system in the future, HDLC protocol was adopted in the system. The system performance was improved by using the communication controller chip and the large data buffer. For reducting the communication problems induced by accumulated noise in up-stream data channels, the system was designed that the different communication channel can be assigned to each proper mass of terminal. The operating software was designed with menu driven user interface and have various functions for the convenience of users. The test result of the implemented system at the experimental network showed good performance and suitability for a coaxial CATV Status Monitoring System.

We discussed the Distributed Control System's design on preface and analyzed time of the real-time communication by using designed system. The DCS proposed in this thesis was implemented to network file system having recovery advantage and shared memory method to access file system of a Remote Station with ease. Also, this system minimized the network delay-time by using the real-time VME147 board. In implemented DCS, the performance analysis of real-time process of a Remote Station was done to get the total time for reak-tune communication from a Remote Station to the Central Station after terminating of process. For the analysis of system performance, we experiented by three steps. Firstly, we measuredthe processing the of LOOP function that real-time CPU convertes to-2,500~10.000 values from the input data of the Analog Interface Card. Secondly, we measured the processing time of the LOGIC function and the LOOP function. Lastly, we measured total processing time for communication from a Remote Station to the Centrol Station.

In this paper, the leaky wave readiation characteristics of a microstrip rectangular patch array is presented. The reflection and transmission characteristics are analyzed using the equivalent transmission line method. Since the leaky wave is generated from the periodic array, using the Floquet'theorem, leaky wave frequency range is predicted and confirmed by the measured reflection and transmission characterstics of the array. A 17 element microstrip patch array at X-Band is designed and tested. Teh scattering Characteristics show good agreement woth those obtained from the equivalent transmission line analysis. The radiatio characteristics at 10GHz using this method show about 3${\circ}$ shift in main lobe angle compared with measured results.

In this paper, by modeling the Multilayer-Multiconductor Transmission Line(MMTL) with the characteristic parameters-effective dielectric constant, eigen modal voltages, characteristic impedances at each mode, pulse propagation characteristics of MMTL network are simulated. Transmission line modelling is performed in frequency domain, then time domain resposes are obtained by transforming the frequency domain response using fast Fourier transform.

The problem of a plane wave impinging upon a semi-infinite paralle-plate waveguide is investigated. The interior fields can be analyzed by converting the initial field into vaveguide modes. Kirchhoff approximation is usually made at the waveguide aperture in the literature. In this paper, a modified approximation is made using the Uniform Gemetrical Theory of Diffraction(UTD). Numerical results show excellent agreement between UTD-supplemented mode-matching solution and UTD solution.

The optical JTC system has the advantage of being applied to the real-time correlation system, but it has some difficulties that its amplitude and phase signals cannot be separately processed. Recently to solve those problems the BPEJTC and HPEJTC systemshaving the same characteristics of that of the POC and POF have been proposed. But there is no quantitive analysis how much the amplitude and phase signals are contributed to the correlation outputs respectively. In this paper, a new ACJTC system based on the conventional ACMF is proposed and discussed through the mathematical analysis. The good correlation discrimination of the proposed system is also analyzed by changing the relative contributions of the phase and amplitude signals for some similar targets. From the successful computer simulation results on the scenario where three same targets are periodically located on the natural backgrround, the possibility of the high performance real-time correlation system based on the optical ACJTC is suggested.

We have developed GaAs power metal semiconductor field effect transistors (MESFETs) for 4.7V operation under 900 MHz using a low-high deped structures grown by molecular beam epitaxy (MBE). The fabricted MESFETs with a gate widty of 7.5 mm and a gate length of 1.0.mu.m show a saturated drain current (Idss) of 1.7A and an uniform transconductance (Gm) of around 600mS, for gate bias ranged from -2.4 V to 0.5 V. The gate-drain breakdown voltage is measured to be higher than 25 V. The measured rf characteristics of the MESFETs at a frequency of 900 MHz are the output power of 31.4 dBm and the power added efficiency of 63% at a drain bias of 4.7 V.

Gain-guided broad-area single quantum well separate confinement heterostructure diode lasers have been fabricated from structures grown by metal organic vapor phase epitaxy. The active layer of the epi-structure is InGaAs emitting 962-965nm and the guiding layer GaAs. The channel width is fixed to 150${\mu}$m and the cavity length varys within the range of 300~800${\mu}$m. For uncoated LD's, the output power of 0.7W has been obtaained at a pulsed current level of 2A, which results about 60% external quantum efficiency. The threshold current density is 200A/cm$^{2}$ for the cavity lengths of 800.mu.m LD's. The stain effect upon the transparent current density has been observed. The internal quantum efficiency is expected to be 88% and the internal loss to be 18$cm^{-1}$. The beam divergence has been measured to be 7$^{\circ}$to lateral and 40$^{\circ}$to transverse direction. finally, 1.2W continuous-wave output power has been obtained at a current level of 2A for AR/HR coated LD's die-bonded on Cu heat-sink and cooled by TEC.

Ohmic contacts between Au and p-HgHg_{0.7}Cd_{0.3}Te$ with low specific contact resistance have been obtained. The contact region of the wafer is first pre-heated for 5 seconds in a rapid thermal processing equipment. The temperature reaches a maximum value of about 200$^{\circ}C$ at the end of the 5 seconds. Next, a thin Au film is formed on the contact region by immersing the sample in AuCl$_{3}$ solution. the sample is then post-annealed in the same condition as the pre-heating after Pb/In pad metals are deposited on the electroless Au contacts. The specific contact resistance measured by transmission line model is 5${\times}10^{-3}{\Omega}cm^{2}$ at 80K. RBS and differential Hall measurement data suggest that the above low resistance ohmic contact is ascribed to surface traps and increased gold diffusion rate.

By using the RAPHAEL 3D inductance calculation program RI3, the PGA package inductance values of INTEL i486 microprocessor have been extracted. The lead frame layouts are drawn using the mentor Boardstation and the output files are converted into the RI3 program input format of RAPHAEL. The power and ground planes of the PGA package are modeled y grid-line structures of single bars. The capacitance valuse of signal lines have been clalculated by using the RAPHAEL 2D/3D capacitance extraction program. The extraced L, C, R values have been converted into the SPICE netlist formats with lumped circuit model for future use in the signal ingegrity analysis.

The PMMA/Ge/AZ trilayer resist decreased proximity effect of backscattering electrons and corrected pattern distoration in order to from deep submicron patterns. In the experiment, the prosiemity effect is decreased by 11% and 30% for the case of 0.9$\mu$m and 1.7$\mu$m AZ, respectively, in trilayer resist compared to monolyer resist. also, the EID of 240$\AA$ Ge film is smaller than that of 500$\AA$ film by 365. 0.1$\mu$m line/space was formed in the 2000$\AA$ PMMA layer with the condition of dose 330${\mu}C/cm^{2}$ and of 150sec of develop time in MIBK : IPA (1:3) developer.

The characteristics of the oxidation prevention layers for the copper metallization were investigated. The thin films such as Cr, TiN and Al were used as the oxidation prevention layers for copper. Ultra thin aluminum films were found to prevent the oxidation of copper up to the highest oxidation annealing temperature among the barrier layers examined in this study. It was found that oxygen did not diffuse into copper through aluminum films because of the aluminum oxide layer formed on the aluminum surface and the ultra thin aluminum film could be a good oxidation barrier layer for the copper metallization.

To resolve thd discrepancy between the existing channel thermal noise theory of MOSFETs and a new theory called the stady-state Nyquist theorem, we have measured the channel thermal noise of specially designed MOSFETs with both uniform and nonuniform channels. the experimental results clearly show that the correct theory of the channel thermal nois in MOSFETs should be the steady-state Nyquist theorem.

In this paper, we first propose a new FPGA routing method in which seversal netw are routed concurrently by applying the readitional maze routing method. We then introduce CMRF (concurrent maze Router for FPGA) which can be used for the routing of FpGAs of symmetrical array type by applying our new routing method. Given a set of nets, the proposed routing method performas the maze propagation and backtracing independently for each net and determines the routing paths concurrently by competition among nets. In CMRF, using this routing method, q nets are selected from the nets to be routed and they are routed concurrently, where q is the user given parameter determined by considering the computing environment. This process is repeated until either all the nets are routed or the remaining unrouted nets fail to their maze propagations. The routing of these nets are completed using the rip-up and rerouting technique. We apply our routing method to ten randomly generated test examples in order to check its routing performance. The results show taht as we increase the value of q, the routing completion rate increases for all the examples. Note that when q=1, our method is similar to the conventinal maze routing method. We also compare CMRF with the CGE method which has been proposed by Brown et.al. For the five benchmark examples, CMRF complete the routing with less wire segments in each connection block than the wire segments needed in the CGE method of 100% routing.

In this paper, we consider the area-minimal implementation of the instruction decoder for microprogrammed processors such as modern CISC-type microprocessor. We formulate it as a constrained output encoding problem and, based on simulated annealing algorithm, propose efficient heuristic solution methods both for PLA and multi-level implementation of the decoder. Experimental results on various examples show that our methods produce, on the average, 10~40% reduction of the number of product terms for the PLA implementations and 9.8~34.4% reduction of the number of literal for the multi-level implementations compared to the results of random encoding method.

this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

Two dimensional interpolation filter for HD-MAC is designed with 1.0 .mu.m CMOS standard cells and verified by logic simulation. The interpolator uses FMH(FIR-Median Hybrid) filter. The median filter, which is the most complicated part of FMH filtre, is simply implemented by modifying Hadian-Sobel algorithm. the filter generates accurately the missed pixel data of luminance and chrominance with the worst case simulation condition at 27MHz clock rates.

This paper describes the design of a neurochip with on-chip learning capability in hardware with multiple processing elements. A digital architecture is adopted because its flexiblity and accuracy is advantageous for simulating the various application systems. The proposed chip consists of several processing elements to fit the large computation of neural networks, and has on-chip learning capability based on error back-propagation algorithm. It also minimizes the number of blobal control signals for processing elements. The modularity of the system makes it possible to buil various kinds of boards to match the expected range of applications.

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.