In this paper, we will propose 4-move ZKIP and its application. Using bit-commitment scheme that is necessary to organize the ZKIP related to NP-Complete problem and WH and WI preserving the property for security under parallel composition of protocols, we will show that the proposed ZKIP is 4-move ZKIP of SAT comparing to 6-move ZKIP of SAT proposed by Brassard. Chaum and Yung, and under claw-free pairs of function the proposed ZKIP is also 4-move ZKIP comparing to 5-move ZKIP proposed by Goldreich and Krawczyk under the same assumption. Moreover we will show the efficiency of the proposed scheme better than Fiat and Shamir's scheme at the points of computational complexity and communication complexity, and also propose the efficient and secure identification scheme against the chosen ciphertext attack, using the proposed scheme.

In a spread spectrum system, the bandwidth and period of spreading code is wide and long, respectively. So it is necessary to make the code acquisition time as short as possible. In particular, serial search code acquisition system requires optimum dwell time for fast acquisition. In this paper, code acquisition time is calculated by varying dwell time. Among them, minimum code acquisition time is chosen and then optimum dwell time can be obtained. Detection probability (P$_{D}$) and false alarm probability (P$_{FA}$) can be obtained by integrating chi-square pdf by numerical analysis. The results are compared with that of gaussian approximation method and then it is concluded gaussian approximation method is not suitable for obtaining optimum dwell time. Computer simulation supports theoretical results.

The bit error probability of Reed-Solomon/convolutional concatenated codes can be more exactly calculated by using a more approximate bound of the symbol error probability of the convolutional codes. This paper obtains the unequal symbol error bound of the convolutional codes, and applies to the calculation of the bit error probability of the concatenated codes. Our results are tighter than the earlier studied other bounds.

This paper presents a mobile measurement technique of the ghost-flutter caused in mobile television reception. The ghost-flutter is caused by timing variation of the television horizontal synchronizing pulse due to frequency selective fading in a multipath propagation environment. The ghost-flutter can be detected by measuring the dynamic timing variation of horizontal synchronizing pulse. Especially, in this paper, a technique for measuring horizontal synchronizing timing fluctuations which cause the ghost-flutter is developed, using a Rubidium oscillator as a time standard with high stability.

Effect of high temperature annealing conditions on Ta$_{2}O_{5}$ thin films was investigated. Ta$_{2}O_{5}$ thin films were deposited on P-type silicon substrates by plasma-enhanced chemical vapor deposition (PECVD) using tantalum ethylate. Ta(C$_{2}H_{5}O)_{5}$, and nitrous oxide. N$_{2}$O. The microstructure changed from amorphous to polycrystalline above 700.deg. C annealing temperature. The refractive index, dielectric onstant and leakage current of the film increased as annealing temperature increased. However, annealing in oxygen ambient reduced leakage currents and dielectric constant due to the formation of interfacial SiO$_{2}$ layer. By optimizing annealing temperature and ambient, leakage current lower than 10$^{-8}$ A/cm$^{2}$ and maximum capacitance of 9 fF/${\mu}m^{2}$ could be obtained.

Ar ions were implanted at 1 MeV into (100)Cz Si wafers with dose of 1 * 10$^{15}$ ions/cm$^{2}$. Damage induced by high energy implantation and its annealing behavior during rapid thermal annealing for 10sec at temperatures from 550 to 1100${\circ}C$ were investigated by crosssection transmission electron microscopy study. It can be clearly seen from the observation that the SPE(Solid Phase Epitaxy) regrowth of the buried amorphous layer induced by ion implantation proceeds from both upper and lower amorphous/crystalline (a/c) interfaces, and the activation energy for SPE from interfaces were both 1.43eV. Misfit dislocation where two interfaces met was formed and it coalesced into the hair pin dislocation in the upper regrown region. At the higher temperature after annealing out of the misfit dislocation, hair pin dislocations showed considerable drop in its bandwidth. However, they were not disappeared even at the temperature 1100${\circ}C$ with the end of range dislocation loops which were formed at the original lower a/c interface.

In this paper, we present a new lifetime prediction model for PMOSFET by using the correlation between transconductance degradation and substrate current influence. The suggested model is applied to a different channel structured PMOSFET, dgm/gm of both SC-PMOSFET and BC-PMOSFET appear with one straigth line about Qbib, therefore, this model is independent of channel structure. The suggested model is applied to a different drain structured SC-PMOSFET. Unlike S/D structured SC-PMOSFET, dgm/gm of LDD structured SC-PMOSFET appears with one straight line about Qb, therefore, this model is dependent of drain structure.

In this paper, both feasible power gain and power added efficiency at the operating center frequency of 12 GHz are stressed to design a power FET with double-heterjunction structure. The variable parameters or the design are the unit gate width, the gate length, the doping density of AlGaAs, the AlGaAs thickness, the spacer thickness, the Al mole fraction, and the GaAs well thickness. The results of simulation for the FET with 1.mu.m gate length show that the power gain and the power added efficiency are 10.2 dB and 36.3% at 12GHz, respectively. An extrapolation of the relation between current gain and unilateral gain yields a 17 GHz cutoff frequency and 43GHz maximum frequency of oscillation. The calculation of the current versus voltage characteristics show that the output power of the device is about 0.62W.

To verify validity of the steady-state Nyquist theorem and the steady-state Nyquist theorem with hot carrier effects in semiconductor devices, we calculate thermal noise in n-i-n structures using both the steady-state Nyquist theorem and the Monte-Carlo method, and compare the results from these two-methods. When the carrier temperature is not far from the lattice temperature, the results from both methods agree with each other very well, but in the hot carrier regime there are some discrepancies. Our results support the argument that for MOSFETs and MESFETs operating in the linear region, the channel thermal noise should be explained by the steady-state Nyquist theorem rather than by the existing theories.

We fabricated 0.3um gate length inverse-T gate MOS(ITMOS) and conventional lightly doped drain oxide spacer MOS(LDDMOS), and studied electrical characteristics for comparison. Threshold voltage of 0.3um gate length device was 0.58 V for ITMOS and 0.6V for LDDMOS. Measured subthreshold characteristics showed a slope of 85mV/decades for both ITLDD and LDDMOS. Maximum transconductance at V S1ds T=V S1gs T=3.3V was 180mS/mm for ITMOS and 163mS/mm for LDDMOS respectively. GIDL current was observed to be 0.1pA/um for ITOMS and 0.8pA/um for LDDMOS. Substrate current of ITMOS as a function of drain current was found to be reduced by a foactor of 2.5 compared with that of LDDMOS.

The growth thickness uniformity of epitaxial layers deposited using a moiecular beam epitaxy system is calculated from the arrangement of molecular beam source and the substrate and the geometric dimensions of the crucible in order to predict the optimum design conditions of the prototype MBE system. The thickness uniformity better than 5% over a 3-inch wafer can be obtained by keeping the distance between the substrate and the crucible's orifice longer than 20cm, the tapering angle of the crucible larger than 6$^{\circ}$, and the angle between the normal to the substrate at the center and the crucible axis as larger as possible. In addition, the growth yield decreases to below 51% as the distance between the substrate and the orifice becomes longer than 25cm.