The analysis of the resonant tunneling based on the exact solution of Schrodinger equations is performed in a single quantum well structure under applied bias. The transmittivity and the net tunneling current density are calculated with Airy function and the boundary conditions which is suggested by Bastard. The results are compared with those from other methods and boundary conditions. From the calculated J-V characteristics for the tunneling current, the dependence of the voltage location showing the first peak current on the various temperatures and Fermi level is investigated. In addition, the wave function within the structure is obtained and compared with that from the flat-potential model.

In this paper, a method for the calculation of 2-dimensional interconnection capacitance for a multi-interconnection signal line in a dielectric region is presented. The numbers of dielectric layers and signal lines are arbitrary. To calculate the capacitance parameter, Boundary Element Method is used, and the dielectric interface and the surface of lines are divided into subsections. The advantages of BEM are small CPU-time and more exact solution due to the directly calculated values of capacitance only at the boundary of domain.It is adopted that the surface capacitance of each subsection assumed constant. The solution of surface charge density and capacitance parameter are calculated in a given domain.

4인치(100) 실리콘 기판상에 센서용 다이아프램을 제조할 때 생기는 식각 현상들을 관찰하고 분석하였다. 115$^{\circ}C$의 "F etch' 용액을 사용하여 300$\mu$ 이상의 깊은 식각을 행하였을 때 식각 표면에 발생하느 식각 결함은 hillock, 반응 생성물, 그리고 횐색 잔유물로 구분될 수 있었따. 특히 hillock의 경우 식각 표면에 부착된 반응 생성물의 밀도나 크기에 관계하여 |111|면들로 이루어질는 피라밋 구조나 사다리꼴 육면체등의 형태를 취함이 확인되었다. 또한 용해된 실리콘의 국부적인 과잉 포활 발생하는 흰색 잔유물의 IR 흡수 스펙트럼을 조사한 결과, Si-N-O 성분에 미량의 h와 C가 포함된 것임을 알 수 있었다. 아울러 식각면을 식각용액에 대해 아래쪽, 위쪽, 그리고 측면을 향하도록 놓았을때 식각 결함의 존재 확률과 분포 그리고 식각율의 분포를 비교한 결과 식각율의 균일성면에서는 하측방향의 자세가, 식각결함의 제거에 있어서는 측면방향의 자세가, 식각결함의 제거에 있어서는 측면방향의 자세가 유리하게 나타났으며 이를 반응조내의 흐름 패턴을 이용하여 해석하였다.

In SFB Process, after 110$0^{\circ}C$ annealing in wet OS12T(95$^{\circ}C$ HS12TO bubbling) atmosphere, the existence of the interfacial oxide film in micro-gap at Si-Si bonding interface was identified. The angle lapping/staining and SEM morphologies of bonding interface showed that the growing behavior of interfacial oxide made a contribution to eliminate the micro-gaps having a width of 200-300$\AA$. In case of the diodes composed of p-n wafer pairs made by SFB processes, the annealed one in wet OS12T atmosphere exhibited a dielectric breakdown phenomena of interfacial oxide at 37-40 volts d.c.

This paper presents the design of a layout processing system that performs circuit and symbolic extraction from hierarchical designs containing arbitrarily shaped layout. The system is flexible enough to deal with various technologies, MOS or bipolar, by providing extraction rules in the form of technology files. In this paper, new efficient algorithms for trapezoidal decomposition of polygon and symbolic path extraction using trapezoidal template are proposed for symbolic extraction. Circuit and symbolic extractor is developed as an integrated design environment of SOLID system.