In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

In this paper, performance of a hybrid direct-sequency/slow-frequency-hopped (DS/SFH) spread-spectrum (SS) system with coherent BPSK modulation is analyzed. The bit error probability is derived over a frequency=-selective rician fading channel in the presence of multiple tone jamming. The fading channel is modeled as the wide-sense stationary uncorrelated scattering (WSSUS) model. Numerical evaluations are presented for some combinations of system parameters. The performance of a hybrid DS/SFH SS system is shown to be inferior to that of a ure DS SS system at low jamming-to-signal power ratio (JSR). At high JSR, the performance of a pure DS SS system is shown to be the smae as the worst case performance of a hybrid DS/SFH SS system.

Spread spectrum method gurantees good performance in digital communication system under multi-path interference and jamming signals. The purpose of this paper is to develop the wireless modem using DS/SS techinque. The transceiver consists of a spread spectrum DQPSK transmitter and a mtching receiver. The system operates with the chipping rate set to 4 Mcps and the number of chips/symbol at 64, making the data rate 62.5 Kbps using QPSK modilation. The receiver section uses a digital matched filter for fast acquisition of burst signals and uses the comparing the BER of proposed system iwth that of narrow bnd system under various additive white gaussian noises. It is showen that the proposed sysem has better performance than narrow band system. When jamming signals is added to the suggested DS/SS system, we also show that the experimental performance (BER) of the suggested wireless modem is almost same as theroretical performance.

In this paper we wanted to implement a reliable ISDN PABX that could maintain the user's voice and data communication services, even when there might be an unexpected system error. In order to implement the fault-tolerance we made this ISDN PABX composed of an active and a standby side by duplicating the main control parts. Whenever a critical error occurs in the active side, it makes side exchange so that the standby side as anew active side continues to proceed the currently active voice or data services. Finally, through the performance evaluation we proved that user's voice or data communication can be serviced without any sense in spite of an system error.

The radiation characteristics of a slot antenna in a plane conductor covered with a miving isotropic plasma layer are analyzed. The radiation null which causes distortion in radiation pattern is explainted by the zero of integrand in an asymptotic integral for radiation fields as a function of the plasma parameter and the plasma velocity. Numerical resutls for a radiation null calculated from various plasma and velocity parameters correspond to the results of two-dimensional problem.

This paper presents a monopulse feed structure with low sidelobe monopulse pattern, which consists of a E-plane corrugated horn and a unfiorm pick-up aperture power divider. Tfhe design methods and epxerimental resutls of the E-plane corrugated feeder are described. Modified hybrid mode analysis and GSM (generalized scattering matrix) methods are introduced to design the E-plane corrugated feed horns. The 24-port corrugated feeder is designed using modified hybrid mode analysis initially and verified using GSM methods. Measurement results show that this feeder has low return loss and sidelobe level at sum and difference channel, respectively.

In this study, when the coherent detector has been developed and manufactured in the receiver of radar system, we have suggested and realized the 'Frequecny-Feedback correction (FFC)' that extracts its errors affecting the performance of radar, such as amplitude imbalances (k), phase imbalance ($\varphi$) between channels and offset votlages and corrects them to improve radar performances. Applying the FFC proposed, we analyzed sthe properties of the coherent detector and compared its perfomances after and before correction procdure. After the correction sequence, the amplitude imbalance was improved upt o 2dB and the phase imbalance over 9$^{\circ}$. The image rejection ratio (IRR), one of the figures of merit of radar system, was made better above 9 dB after correcting the coherent detector which possessed 23 dB before.

In this paper, a modifed TE$_{113}$/TM$_{012}$ triple-mode bandpass filter is implemented by using a modified inter-cavity iris in which the number of slots are reduced upto 50%. In a coventioanl iris two prirs of slot apertures are used to independently couple three resonant modes between two adjacent cavities. However, if transverse magnetic polarizability of a pair of veritcal slot apertures is used to control weak horizontal TE$_{h}$-TE$_{h}$ mode coupling, the width of novel iris slots would substitute for the slot length of the conventional iris, causing to eliminate the horizontal slot apertures. The measured data of two filters, which are the modified filter and ocnventional one, are compared. Experimental result shows that the characteristics of the novel triple-mode filter matches well that of the conventional filter.

in urban cross-roads with dense buildings, receiving power and delay spread were computed when doing these, we were able to develope codes to be executed in a very fast time by combining image method and algorithm for propagation paths compairing with ray launching technique. And receiving power and delay spread could be viewed in 3-dimensional picture by virtue of computing electric fields in arbitrary receiving point. For numerical computation, receiving power of wide and anrrow band and delay spread were computed, and extension method of ray numbers was facilitated for handling infinite number of rays.

Periodically slotted dielectricalloy filled parallel-plate waveguide as a leaky wave antenna is designed and fabricated at the center frequency of 10.0GHz. The antenna was fed by use of a hog-horn structure. The hog-horn and the two side walls and the lower plate of parallel-plate waveguide were fabricated form duralumin. The upper plate of parallel-plate waveguide with 48 periodic slots was made of copper plate of 1mm thickness. The dielectric material inside the parallel-plate waveguide was chosen to be paraffin. The experimental radiation pattern for the fbricated antenna was compared with the theoretical results for the finite periodic structure.

Because of the novel characteristics such as chemical stability, hardness, electrical resistivity and thermal conductance, diamond-like carbon (DLC) film is a suitable materials for the passivation layers. For this purpose, DLC films are synthesized under various conditions and are characterized. Adhesive stregth is excellent and increased with the increase of the hydrogen gas flow rate. The resistivity of approximately 5.3X10$^{8}{\Omega}{\cdot}cm$ is measured by automatic spreading resistance probe analysis method. The thermal conductivity of DLC films is superior to that of PSG oxide and improved by increasing the hydrogen gas flow rate. The patterning techniques of the DLC films is developed using the lift-off and RIE methods to form 5${\mu}$m line. Finally, power transistor with the DLC film as passivation layer is fabricated and analyzed. The test result shows the improsved long-term stability and higher breakdown voltage.

We have invetigated the characteristics of thermal instability of Co-silicides annealed at 850$^{\circ}$C ~ 1000$^{\circ}$C for 10~90 minutes in a furance with N$_{2}$ ambient. In our experiments, Co-silicides and Co/Ti bilayer silicides were formed by depositing (Co, Ti) films on the clean Si substrates in an E-beam evaporator and performing the RTA annelaing. The sheet resistances of Co-silicides formed form Co exhibited the nearly constant value under the post-annealing time above 900$^{\circ}$C showing the increase of 30% and 60% under the conditions annealed at 900$^{\circ}$C and 1000$^{\circ}$C for 30minutes. On the other hand, there were no remarkable changes in the sheet resistance sof Co-silicides formed form Co/Ti bilayer under the post-annealing conditons below 1000$^{\circ}$C.

Impact ionization model in GaAs has been presented by modified keldysh formula with two sets of power exponent of 7.8 and 5.6 in study. Impact ionization rate is derived from fermil's golden rule and ful lenergy band stucture based on empirical pseudopotential method. Impact ionization rates show anisotropic property in low energy region (<3eV), but isotropic in high energy region (3>eV). Full band monte calo simulator is coded for investigating the validity of the GaAs impact ionization model, and validity is checked by comparing impact ionization coefficients with experimental values and ones in anisotropic model. Valley transitions to energy alteration are explained by investigating electron motion in brillouin zone for full band model to electric field variation.

In the WKB analysis, we propose the new forms of the trial eigenfunctions which not only converge at the turning points but also approximate to the conventional WKB solutions away from the turning points. The eigenvalue equation of multiple waveguides with graded index profile are derived by using the proposed WKB analysis and the transfer matrix method. The drived equation sare represented in the recursive form. The results of the eigenvalue equation sare comapred with those of the FDM, one of the well-known computational methods, for a three-waveguide coupler.

In this paper, we propose an algorithm to solve the problem of placement of rectangular blocks whose sizes and shpaes are pre-determined. The proposed method solves the placement of many retangular blocks of different sizes and shapes in a hierarchical manner, so as to minimize the chip area. The placement problem is divided into several sub-problems: hierarchical partioning, hierarchical area/shape estimation, hierarchical pattern pacement, overlap removal, and module rotation. After the circuit is recursively partitioned to build a hierarchy tree, the necessary wiring area and module shpaes are estimated using the resutls of the partitioning and the pin information before the placement is performed. The placement templaes are defined to represent the relative positions of the modules. The area and the connectivity are optimized separately at each level of hierachy using the placement templates, so the minimization of chip area and wire length can be achieved in a short execution time. Experiments are made on the MCNC building block benchmark circuits and the results are compared with those of other published methods. The proposed technique is shown to produce good figures in tems of execution time and chip area.

In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

This paper descrisbes the implementation of a 20D DCT that can be used for video conference, JPEG, and MPEG-related applications. The implemented DCT consists of two 1-D DCTs and a transposed memory between them, and uses ROM-based multipliers instead of conventional ones. As the system bit length, the minimum bit length that satisfies the accuracy specified by the ITU standard H.261 was chosen through the simulations using the C language. The proposed design uses a dual port RAM for the transposed memory, and processes two bits of input-pixel data simultaneously t ospeed up addition process using two sets of ROMs. The basic system architecture was designed using th Synopsys schematic editor, and internal modules were described in VHDL and synthesized to logic level after simulation. Then, the compass silicon compiler was used to create the final lyout with 0.8um CMOS libraries, using the standard cell approach. The final layout contains about 110, 000 transistors and has a die area of 4.68mm * 4.96mm, and the system has the processing speed of about 50M pixels/sec.