In this paper as a new approach for real-time multitarget tracking, a hybrid OptoNeural multitarget tracking system based on optical BJTC and neural networks data association algorithm is suggested. In the proposed hybrid tracking system, an optical BJTC is introduced as a preprocessor to reduce the massive input target data into a few correlation peak signals and then the neural networks data association algorithm is used for the massively parallel data association between measurement signals and targets in real-time. Finally, new hybrid type OptoNeural target tracking system is constructed and then some experimental results on multitarget tracking is included. The real-time implementation method of the proposed hybrid system is also discussed.

In this paper, the single round type and the multilayered type actuator using PZT powders were manufactured and their piezoelectric, displacement and time response characteristics were investigated. In the single round type actuator, the piezoelectric coefficient and the displacement increased with sintering temperature. In the multilayered actuator, the piezoelectric coefficient and the displacement increased with the layered number. In ten layered case, the piezoelectric coefficient and the displacement were higher over three times and six times than those of the single round type, respectively. At the voltage applied, the response velocity of the multilayered type was higher over two times than that of the single round type.

An 8-bit 2-stage pipelined current mode A/D converter is designed with a new architecture, where the wideband track-and-hold amplifiers which have 2 integrators in parallel sample input signal twice per clock cycle. The conversion speed of the A-D converter is two times faster than that of conventional pipelined method. The converter is designed to be operated at the power supply voltage of 3.3V with the input dynamic range of 0-256$\mu$A. HSPICE simulation results show the performance of up to 55Msamples/s and power consumption of 150mW with the parameters of ISRC $1.5\mu$m BICMOS process. The chip area is 3${\times}4mm^{2}$.

We experimented on memory multichip modules to increase the packing density of memory devices and to improve their electrical characteristics. A 128K$\times$8bit SRAM module was made of four 32K$\times$8bit SRAM memory chips. The memory multichip module was constructed on a low-cost double sided PCB(printed circuit boared) substrate. In the process of fabricating a multichip module. we focused on the improvement of its electrical characteristics. volume, and weight by employing bare memory chips. The characteristics of the bare chip module was compared with that of the module with four packaged chips. We conducted circuit routing with a PCAD program, and found the followings: the routed area for the module with bare memory chips reduced to a quarter of that area for module with packaged memory chips. 1/8 in volume, 1/5 in weight. Signal transmission delay times calculated by using transmission line model was reduced from 0.8 nsec to 0.4 nsec only on the module board, but the coupling coefficinet was not changed. Thus, we realized that the electrical characteristics of multichip packages on PCB board be improved greatly when using bare memory chips.

CMOS LCD driving circuits using poly-Si TFT have been designed and basic blocks including test patterns have been fabricated. Column driver drives the pixels by block because polu-Si TFT can not operate at the speed of video signal. Row driver has mode selection circuit which can select a mode between interlacing mode and non-interlacing mode. Experimental results show shift register can operate at 1MHz colck frequency with 4pF load.

We investigated theoretically the current-voltage characteristics of resonant tunneling diodes with a single quantum well structure. using a self-consistent method. This method is a numerical analysis which is able to include the effects of the undoped spacer layer and the band bending by charge accumulation and depletion on the contact layers which have not been considered in the flat-band model reported by Esaki. so that it is better suited to explain experimental results. The structure used is an $AL_{0.5}Ga_{0.5}AS/GaAs/Al_{0.5}Ga_{0.5}AS$ single quantum well. In this work. we estimate the theoretical current-voltage characteristics of the same structure, and then, the dependence of the current-voltage curves on the thickness of undoped spacer layers sandwiched between the barrier and highly n-doped GaAs contact layer.

This paper describes the design of a high-level synthesis system. SODAS-VP. which automatically generates hardwares executing operation sequences in pipelined fashion.Target architecture and clocking schemes to drive pipelined datapath are determined, and the handling of pipeline hazards which degrade the performance of pipeline is considered. Partitioning of an operation into load, operation, and store stages, each of which is executed in partitiones control step, is performend. Pipelinecl hardware is generated by handling pipeline hazards with internal forwarding or delay insertion techniques in partitioning process and resolving resource conflicts among the partitioned control steps with similarity measure as a priority function in module allocation process. Experimental results show that SODAS-VP generates hardwares that execute faster than those generated by HAL and ALPS systems. SODAS-VP brings improvement in execution speed by 17.1% and 7.4% comparing with HAL and ALPS systems for a MCNC benchmark program, 5th order elliptical wave filter,respectively.

In the automatic transistor sizing with computer for optimizing delay and the chip area of CMOS digital circuits, conventionally either a mathematical method or a heuristic method has been used. In this paper, we present a new method of transistor sizing, a sort of combination of the above two methods, in which the mathematical method is used for sizing of critical paths and the heuristic method is used for desizing of non-critical paths. In order to reduce the overall problem dimension, a basic block called an extended stage is introduced which includes a basic stage, parallel transistors and complementary part. Optimization for multiple critical paths is formulated as a problem of area minimization subject to delay constraints and is solved by the augmented Lagrange multiplier method. The transistor sizes along non-critical paths are decreased successively without affecting the critical path delay times. The proposed scheme was successfully applied to several test circuits.

A New environment SENSATION for circuit optimization and statistical analysis has been developed. It provides real time simulation and includes automatic algorithms to assist for reaching optimal solution. Furthermore, statistical analysis environment is presented which aids in Monte Carlo analysis. worst case corner analysis, and sensitivity analysis. These capabilities faciliate the characterization of the effects of several operating conditions and manufacture process paramenters on the design performances. We verify that the proposed methods can obtain the optimal solution of the objective function through several experimental results.