In this paper, we propose over-reporting avoidance scheme which avoids congestion of network traffics by adjusting managed system's over-reporting, on the OSI network management model which reports events from managed system to managing system. In case of reporting events from managed system to managing system, management traffic concentration occurs, and it causes over-loading on the managing system and congestion on the network. This scheme takes advantage of feedback from managing system to managed system. Managed system transmits event reports as much as maximum event pertime allocated to itself to managing system, and it sets it's management variables to LOCK state and stops event reports as Threshold time is reached. At the time, managing system directs event reports again by using M-set primitive with referring it's status. With this scheme, distributed processing, dynamic network adaptation, convergence of optimal operation point is possible. In addition to it, a fairness is assured. In order to detect characteristics of the Unary feedback over-reporting avoidance scheme. It is observed a control capability of the event reporting and fairness of each nodes through measuring. ThresholdTime value. It is measured a number of mean activating nodes and maintained time of LOCK state according to event reporting load, and also measured lost ratio of management packet, queuing delay in managing system, and goodput to observe effects of general packet load. Binary feedback scheme. Unary feedback overreporting avoidance scheme and raw scheme on the OSI network management system each are compared and analyzed, and finally proved that the scheme proposed in this study performs better.

New decoding algorithm of double-error-correction Reed-Solmon codes over GF(2$^{8}$) for optical compact disks is proposed and decoding algorithm of RS codes with triple-error-correcting capability is presented in this paper. First of all. efficient algorithms for estimating the number of errors in the received code words are presented. The most complex circuits in the RS decoder are parts for soving the error-location numbers from error-location polynomial, so the complexity of those circuits has a great influence on overall decoder complexity. One of the most known algorithm for searching the error-location number is Chien's method, in which all the elements of GF(2$^{m}$) are substituted into the error-location polynomial and the error-location number can be found as the elements satisfying the error-location polynomial. But Chien's scheme needs another 1 frame delay in the decoder, which reduces decoding speed as well as require more stroage circuits for the received ocode symbols. The ther is Polkinghorn method, in which the roots can be resolved directly by solving the error-location polynomial. Bur this method needs additional ROM (readonly memory) for storing tthe roots of the all possible coefficients of error-location polynomial or much more complex cicuit. Simple, efficient, and high speed method for solving the error-location number and decoding algorithm of double-error correction RS codes which reudce considerably the complexity of decoder are proposed by using Hilbert theorems in this paper. And the performance of the proposed decoding algorithm is compared with that of conventional decoding algorithms. As a result of comparison, the proposed decoding algorithm is superior to the conventional decoding algorithm with respect to decoding delay and decoder complexity. And decoding algorithm of RS codes with triple-error-correcting capability is presented, which is suitable for error-correction in digital audio tape, also.

An analytic approach to wide-band amplification using simplified equivalent MESFET modeling has enabled an ultrabroad-band flat-gain amplifier from DC to microwave. The developed lossy-match ultrabroad-band amplifier operates as a RC coupled circuit in the low-frequency range and lossless impedance matching circuit in the microwave frequency range with gain compensation circuits. The reduced gain caused by external resistors is compensated using 2-stage cascade amplification, and the gain of designed unit is 12.5.+-.1dB from the vicinity of DC to 7GAz. The experimental gain characteristics are good agreement with computer simulated results. The input and output VSWRs are measured under 2:1 over the operating frequency range, and the gain goes down over 15dBrange with various gate bias voltages.

Effects of incident beam position and intensity on self-pumped optical phase conjugation are presented using barium titanate as an optical phase conjugator. Depending on the position of incident beam, the crystal used consists of four major operating regions: irregular pulsing, regular pulsing, stable phase conjugation, and unstable oscillating regions. In the second region, the pulsing frequency and amplitude of phase conjugate beam are proportional to I$_{in}$ and I$_{in}^{0.85}$, respectively, where I$_{in}$ is the incident beam intensity. In the fouth region, the rising time and intensity of the first-generated pulse are proportional to I$_{in}^{0.92}$ and I$_{in}^{0.81}$, respectively. A frequency shift by beam fanning is also discussed by observing interference pattern from an interferometer.

Fluttering ghost which is the most severs picture impairment in mobile TV reception under multipath fading environments can be detected by measuring the dynamic variation of the synchronizing pulse timing. And also, the occurrence-stucture of fluttering ghost are directly correlated with the multipath parameters. This paper describes the quantitative evaluating method of the mobile TV pictures impaired by multipath parameters by means of the spectral analysis of synchronizing timing fluctuation. The ghost-flutter curve derived from the spatial amplitue spectrum of synchronizing pulse timing fluctuation express well the spatial variation characteristic, and it has been found to be the quantitative evaluating measure of picture impairment in mobile reception. A correspondence between the ghost-flutter curve (and/or index) and picture quality opinion test results is established.

The interface properties of Fluoride/GaAs structures were investigated. It was foung that rapid thermal annealing(RTA) typically 800-850$^{\circ}C$for 1 min, was useful for improving the interface properties of that structures. The analysis by means of SIMS indicated that interdiffusion of each constitutional atom through the interface was negligible. The interfacial atom bonding model for RTA treatment was proposed. Bases on these results, inversion-type GaAs MISFET was fabricated using standard planar technologies.

In many practical applications of systolic array, it is common that the problem size(n) is larger than the array size(M). In this case, the problem has to be partitioned into block to fit into the array before it is processed. This paper presents a problem partition method for dynamic programming and 2-dimensional systolic array suitable for it. Designed array has two types of array configur-ation for processing the partitioned problem. The queue is designed for storing and recirculating the intermediate results in the correct location and time. The number of processing elements and queues required are M(3M+1)/2, 4M respectively. The total processing time is 2(M+1)+(n+10M+3)(n/M-1)(n/M-1)/6.

We present a self-consistent, 2-dimensional solution of the Poisson and Sch rodinger equation based on the finite difference method with a nonuniform mesh size for a AlGaAs/GaInAs/GaAs HEMT devide. During the interative self-consistent calculation, however, we calculate Schrodinger equation only a some region of device, not a fully region in order to save the moemory and the speed-up of computation, and then use the approximated data for the other region using by a interpolation method with a given values. Also we adopt the proper matrix transformation method that allows preservation of the symmetric, form of the discretized Schrodinger equation, even with the use of a nonumiform mesh size, therefor, can reduce the computation time. We calculate the wavefunction, eigenstates and the electron concentration uat channel layer nder the thermal equilibrium and the biased conditions, respectively. Also,these parameters are used to solve 2-dimensional tdistribution of potential in he entire region of device. It is proved that the method is very efficient in finding eigenstages extending over relatively large spatial area without loss of accuracy. So, it can be used rather easily in any sarbitrary modulation doped utucture.

In this paper, a simple Ebers-Moll Model for the heterojunction bipolar transistor is presented. Using the model structure for the npn type HBT, the current-voltage characteristics was analyzed. And from the obtained terminal currents, the Ebers-Moll equations were derived. Then substituting the physical parameters for heterojunction to those for homojunction, this model would be used to analyze the characteristics of single and/or duble heterojunction HBT's. And directly relating model parameters to device parameters, it would be also used to optimize the characteristics of HBT's. The simulated results using this model were in good agreement with experimental data.

A noise simulation software is developed to estimate crosstalk and reflection noise in multi-layer printed circuit boards having upto 20 layers and carrying signals of 100 MHz range. The simulation software can handle up to 1000 nets yielding accurate noise value associated with each net. The calculation results can be used to build optimal printed citcuit boards used in high speed computers and telecommunication equipments.

A new switchbox router, called CONQUEROR, is proposed in this paper. The proposed CONQUEROR efficiently routes large switchbox routing area using divide-and-conquer technique. The CONQUEROR consists of three phases` namely, partition of large routing area and assignment of optimal pins of sub-area, detailed routing of each sub-ared, reassignment of pins after rip-up. First, large switchbox routing area is partitioned into several sub-areas and each sub-area contains 4-6 detailed grids. Then pins are assigned on boundary of sub-area by the estimated weight. Secondly, when global pin assignment is completed on all sub-areas, each sub-area is routed using detailed router. Also, detailed routing consists of three pases` layerless maze routing, assignment of layer using coloring, and rip-up and reroute. Lastly, if detailed routing of any sub-area fails,reassignment of pins after rip-up is invoked. Detailed routing is performed for the failed sub-area again. Benchmark test cases have been run, and on all the benchmark data known in the literature CONQUEROR has performed as well as or better than existing switchbox routers.

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

A mechanism for collision detection in general animation system is necessary to prevent the interpenetration among multiple objects. On the other hand, a dynamic simulation system which is a part of animation system simulates realistic motions using dynamics after the collision, which is called collision response. In this paper, a method for reducing the CPU time for collision detection by removing redundant calculations and object sorting is proposed. A dynamic simulation system including collision detection and response function was implemented to demonstrate the proposed methods, where the input data as elasticity, friction, gravity, object shape, external force and external torque are given by the user. The system simulates motions of multiple objects using dynamics, and generates the wireframe display.

Partitioning is an important step in the hierarchical design of very large scale integrated circuits. In this research, a new effective partitioning algorithm based on 2-level hierarchy is presented. At the beginning, clusters are formed to reduce the problem size. To overcome the weakness of the iterative improvement techniques that the partitioning result is dependent on the initial partitioning and to consistently produce good results, the cluster-level partitioning is performed several times using several sets of parameters. Then the best result of cluster-partitioning is used as the initial solution for lower level partitioning. For each partitioning, the gradual constraint enforcing partitioning method has been used. The clustering-based partitioning algorithm has been applied to several benchmark examples and produced promising results which show that this algorithm is efficient and effective.