In this paper, we analyzed the packet blocking probability of a finite buffer in a network interface unit. In general, a network interface unit which provides a means of interface between the network and computer has a microprocessor and a protocol processor for the network access protocols. It also has a receive buffer for the arriving packets from the network which is served by the microprocessor with service interruption by the protocol processor. In this paper, we modeled the receive buffer as a discrete time server with service interruption, and obtained the packet blocking probability using the mini-slot approximation.

Key stream generator consisting of several linear feedback shift registers with a nonlinear combining function have been applied in stream cipher system. Most of the papers until now have been focusing on correlation atack and analysis of key stream generator with nonlinear combining function. Given some part of key stream sequences. We can generate identical output sequences with original key stream sequences if the feedback connection and the maximum order of nonlinear combination function are known.

This paper presents the generalized method of the prediction of the LOS propagating characteristics in an urban microcell by using theray tracing technique. Whereas the received power is calculated by the finite number of pths, 4~10, on an urban steet, the RMS delay spread is comuted by using the sufficient rays of convergence. To take into account the infinite number of paths the technique of the numbering scheme of image antennas was presented by using the rectangular pulse. As to this the existing restriction of the finitte number of paths was relaxed. based on the method of extending the number of paths and the canyon model the received power and RMS delay spread are computed and their differences according to the number of paths are compared at the frequencies of both 1GHz and 2GHz, respectively.

This paper proposes a new UPC(usage parameter control) mechanism that varies the token generation rate of leaky bucket by observing virtual buffer, thus achieving an improvement of performance. An acceptance of a call in B-ISDN is determined by call admission control. A UPC that polices the agreed traffic parameters of a call and takes appropriate actions to prevent congestion in networks. The cell loss probability of conventional UPC is far from that of ideal UPC. The proposed mechanism has a better policing ability and response time for nonconforming call. The proposed mechanism uses ON-OFF model as input traffic. The results of simulation show the efficiency of the proposed mechanism.

Hybrid decision decoding for the extended hamming codes without retransmission, which is a combination of hard and soft decision decoding, is proposed and its performance is analyzed in this paper. As results, hybsrid decision decoding shows a little bit higher residual bit error rate than soft decision decoding. However, as the size of the extended hamming code increases, the difference of th enumber of comparisons increases further. In addition, hybrid decision decoding shows almost same residual bit error rate as hard decision decoding with retrassmission and shows much lower residual bit error rate than hard decision decoding without retransmission.

In this paper, we studied channel assignment and handover schemes for the indoor microcell systems. For efficient frequency spectrum reuse we proposed the high quality reassignment (HQR) scheme. Proposed HQR scheme tries to keep the reuse distances small by monitoring C/I of channels being used. To assign a channel for a new or handove call, the scheme checks C/I of all available channels. Then HQR assigns the channel that has C/I near the threshold value, A_TH. The scheme also checks C/I of ongoing calls and continuously reassigns a new channel when needed. It attempts handover not only when C/I gets below a handover threshold value, HO_TH, but also when C/I becomes above a high quality reassignment threshold, H_TH. The performance of the proposed HQR scheme was analyzed by a computer simulation configuraed. The performance of the scheme was also analyzed for various threshold values selected and the results are presented in this paper. The results show that HQR scheme perfomrs better than the scheme adopted for DECT.

This paper proposes the channel-access protocol suitable to a very high speed photonic WDM network with star configuration, which can provide a high channel utilization and insensitivity to the propagation delay. The proposed protocol employs a control channel and a simple status table to deal with the propagation delay which has been a major limiting factor in the performance of the very high speed optical communication networks. The control channel transmits control information in order to reserve access on data channels, and each node constitutes a status table after the reception of control pckets which holds information about the availbility of destination node and data channel. The proposed protocol is insensitive to the propagation delay time by removing necessity of the retransmission and by allowing parallel transmission of control packet and data packets. It is proved in analysis and discrete event simulation that the proposed protocol is superior in throughput and mean delay, especially at the high load conditions compared to the existing high speed channel-access protocols.

In this paper, we propose two types of WDMA protocol for multi-wavelength optical networks that have a dedicated control channel. Protocol type I is designed for the case that the number of nimislots is less than the number of nodes (La${\ge}$M). Proposed protocols employ the aging scheme to guarantee a fairness in the process of channel allocation. The perfomrance of proposed protocols are evaluated in terms of throughput and delay with variations in offered load. Simulation results show that the proposed protocols have superior performance to conventional protocols.

We analyzed wideband propagation characteristics of a microstrip transmission line based on FR-4 composite substrate using the wideband complex dielectric constant model and the phenomenological loss equivalence method. The loss calculated by constant relative permittivity and loss tangent is greatly overestimatd compared to that calculated by the frequency-dependent complex relative permittivity. This wideband analysis can be helpful to characterize high-speed and high-density transmission lines associated with the wideband dielectric characteristics and shows that the FR-4 composite substrate has high potential of high frequency circuit applications in terms o fthe propagation loss.

Solid-state devices can be directly integrated with a planar antenna to form active antenna elements. In this paper, the voltage controlled oscillator (VCO) is designed and fabricated at 2.4 to 2.5 GHz using a microstrip patch antenna. A varactor diode is used as avariable reactance. The predicted frequency tuning range of the VCO is 2.448 to 2.498 GHz in the design procedure and the fabricated VCO has 2.446 to 2.498 GHz frequency tuning range when the varactor tuning voltage is varied from 0 to 11V. Transmitted power output of the patch antenna which serves both as a rsonator and a radiating element for VCO is about 18 mW over this tuning range.

We have studied the effects of La concentration on the optical and electrical properties of lead lanthanum titanate (PLT) thin films by using sol-gel method. Both the optical and electrical properties are greatly affected by the La concentration. The refreactiv eindices of the films varied from 2.23 to 1.93 with varying La concentration in the range from 15 to 33 mol%. The dielectric constants of the films vary form 340 to 870 with varying La concentration in the range form 15 to 33 mol%. Hysteresis loop becomes slimmer with the increase of La concentration form 15 to 28mol% and little fatter again with the increase of La concentration form 28 to 33 mol%. Among the films investigated in this research, PLT(28) thin film shows the best dielectric properties for the application to the dielectrics of ULSI DRAM's. At the frequency of 100Hz, the dielectric constant and the loss tangent of PLT(28) thin films are 940 and 0.08 respectively. Its leakage current density at 1.5${\times}10^{5}$V/cm is 1${\times}10^{-6}A/cm^{2}$. The comparision between the simulated and the experimental curves for the switching transient characteristics shows that PLT (28) thin films behaves like normal dielectrics.

고농도로 붕소가 도핑된 실리콘층 내에 존재하는 부정합 전위는 웨이퍼 가장자리에서 발생됨을 알았으며, 이 층을 도핑되지 않은 영역으로 둘러쌓음으로써 부정합 전위가 억제된 고농도로 붕소가 도핑된 실리콘층을 형성할 수 있었다. 이를 이용하여 부정합 전위가 없는 고농도로 붕소가 도핑된 실리콘 멤브레인을 제작하였으며, 이 멤브레인의 표면 거칠기 및 파괴 강도 그리고 잔류 인장 응력을 각각 20$\AA$ 1.39${\times}10^{10}dyn/cm^{2}$ 그리고 2.7${\times}10^{9}dyn/cm^{2}$로 측정되었다. 반면에 부정합 전위를 포함하는 기존 멤브레인은 각각 500$\AA$ 8.27${\times}10^{9}dyn/cm^{2}$ 그리고 9.3${\times}10^{8}dyn/cm^{2}$로 측정되었으며, 두 멤브레인의 이러한 차이는 부정합 전위에서 기인함을 알았다. 측정된 두 멤브레인의 Young's 모듈러스는 1.45${\times}10^{12}dyn/cm^{2}$로 동일하게 나타났다. 또, 도핑 농도 1.3${\times}10^{12}dyn/cm^{3}$에 대한 고농도로 붕소가 도핑된 실리콘의 유효 격자 상수 및 기존 멤브레인의 평면적 격자 상수 그리고 기존 멤브레인 내의 부정합 전위의 밀도는 각각 5.424$\AA$ 5.426$\AA$ 그리고 2.3${\times}10^{4}$/cm 로 추출되었으며, 붕소가 도핑된 실리콘의 부정합 계수는 1.04${\times}10^{23}$/atom으로 추출되었다. 한편 별도의 추가적인 공정없이 일반적인 에피 성장법을 사용하여 고농도로 붕소가 도핑된 실리콘층 위에 부정합 전위가 없는 에피 실리콘을 성장시켰으며, 이 에피 실리콘의 결정성은 매우 양호한 것으로 밝혀졌다. 또 부정합 전위가 없는 에피 실리콘에 n+/p 게이트 다이오드를 제작하고 그 전압-전류 특성을 측정한 결과 5V의 역 바이어스에서 0.6nA/$cm^{2}$의 작은 누설 전류값을 나타내었다.

Thin film Ba$^{0.7}Sr^{0.3}TiO^{3}$ (BST) capacitors were fabricated on SiO$_{2}$/Si substrates by RF magnetron sputtering method and characterized at microwave frequencies ranging from 40 MHz to 1GHz to examine the dielectric dispersion of the capacitors. The BST thin films were electrode material of BST thin films capacitor which is known as one of the best electrode materials for BST films. 50$\AA$-thick titanium (Ti) layers were introduced to increase adhesion between bottom Pt and SiO$_{2}$. The leakage current density of the capacitors was about 1.7${\times}10^{7}A/cm^{2}$ at 1.5V and the dielectric constant was about 140 at 1MHz. Microwave measurement patterns having a coplanar waveguide type were fabricated and their S parameters were measured using network analyzer. After de-embedding parasitic components in microwave measurement patterns nearly frequency-invariant dielectric constant of about 120 was extracted in the measurement range of 40 MHz to 1 GHz.

In an effort to learn more about the reaction mechanisms which lead to the compound nucleation at the interface of cobalt and silicon, electrical noise properties has been investigated for cobalt thin films deposited on silicon substrates by the electron beam evaporation and rf sputtering techniques. Microstructural variations at the Co/Si interfaces have been observed by transmission electronmicroscopy. Amorphous structures are observed at the Co/Si interfaces for samples whose cobalt thicknesses are less than 4nm and a polycrystalline compound nucleation has been occurred for thicker films. 1/f noise power same samples, and the spetral density has been normalized. The amplitude of 1/f noise power spectral density shows a gradual increase as the cobalt thickness is increased, and the amplitude has dropped abruptly after the compound nucleation. The variations of the noise parameters areassumed to be an indiction of the phase transformation along the nucleation reaction path, and amplitude has been interpreted as instabilities of the Co/Si interfacial structures.

Inthis apper wa analyzed the channel-hot-electron programming characteristics of the single-poly EEPROM with different control gate and drain structures. The single-poly EEPROM uses the p$^{+}$/n$^{+}$-diffusion in the n-well as a control gate instead of the second poly-silicon. The program and erase characteristics of the single-poly EEPROM were verified using the two-dimensional device simulator, MEDICI. The single-poly EEPROM was fabricated using 0.8$\mu$m ASIC CMOS process, and its CHE programming characteristics were measured using HP4155 parameteric analyzer and HP8110 pulse gnerator. Especially we investigated the CHE programming characteristics of the single-poly EEPROM with the p$^{+}$-diffusion or n$^{+}$-diffusion in the n-well as a control gate and the LDD or single-drain structure. The single-poly EEPROM with p$^{+}$-diffusion in the n-well as a control gate and single-drain structure was programmed to about VT$\thickapprox$5V with VDS=6V, VCG=12V(1ms pulse width).th).

The output of the mach-zehnder optical fiber interferometer varies with birefringences existing in the figer arms. New equations experessing for the visibility of the mach-zehnder interferometer were derived in terms of a number of parameters related to the birefringences, the input SOP and the optical losses. Based on the equations the visibility of the interferometer was simulated in different cases. Some maximum visibility conditons were also presented.

Bonding wires for high frequency device packaging have dominant parasitic inductances which limit the performance of semiconductor lasers. In this paper, the inductance sof bonding wires are claculated by the method of moments with incorporation of ohmic loss, and the wideband modulation characteristics are analyzed for ddifferent wire lengths and structures. We observed the modulation bandwidth for 1mm-length bonding wire lengths and structures. We observed the modulation bandwidth for 1mm-length bonding wire is 7 GHz wider than that for 2mm-length bonding wire. We also observed th estatic inductance calculation results in dispersive deviation of the parasitic inductance and the modulation characteristics from the wideband moment methods calculations. The angled bonding wire has much less parasitic inductance and improves the modulation bandwidth more than 6 GHz. This calculation resutls an be widely used for designing and packaging of high-speed semiconductor device.

In reconfiguration of systolic arrays, a potential disadvantage is that in the PRESENCE of consective faulty PE's logically connected PE's may be far apart, requiring the reduction of clock speed and thus reducing throughput of the array. Thus it is fundamental tokeep locality of interconnections as high as possible even after reconfiguration and to make reconfiguration implemented in the simple routing devices. However requirements of locality and simplicity mean that reconfiguring capability is limited. This paper deals iwth the issue of developing efficient method for reconfiguration of 2-D systolic arrays which can be achieved high reconfiguration rate, with the two conditions satisfying using concept of pseudo faulty processing element. Applying this concept to reconfiguration of systolic array, we have found similar condition. The simulation shows that recomfiguration rates are 97%, 84% when N faults ocurs on the N$\times$N array n case of N=5, 8 respectively.

In this paper, a new structure that can do fault detection and location of digial logic circuits more efficiently using current testing techniques is proposed. In the conventional method, observation point for steady state power supply current was only one, but in the proposed method more fault classes are divided for fault detection and location through the ovservation of steady state power supply current at two points. Also, it is shown that this structure can be easily applied in detection of stuck-open fault which is not easy to do testing with conventional current testing techniques. In the presented mehtod, an extra trasnistor is used, and current path is made compulsorily in the CMOS circuits in which no current path can be established in steady state, then it can be known that stuck-open tault is in the MOS transistor on the considering current path, if this path disappears due to stuck-open fault. The validity and the effectiveness is shwon, thorugh the SPICE simulation of circuits with fault and the current path search experiment using current path search program based on transistor short model wirtten in C language on SUN sparc workstation.

Beause BiCMOS logic circuits consist of CMOS part which constructs logic function and bipolar part which drives output load, the effect of short faults on BiCMOS logic circuits represented different types from that on CMOS. This paper proposes new test method which detects short faults on BiCMOS logic circuits using current path graph. Proposed method transforms BiCMOS circuits into raph constructed by nodes and edges using extended switch-level model and separates the transformed graph into pull-up part and pull-down part. Also, proposed method eliminates edge or add new edge, according ot short faults on terminals of transistor, and can detect short faults using current path graph that generated from on- or off-relations of transistor by input patterns. Properness of proposed method is verified by comparing it with results of spice simulation.

This paper presents a new scheduling algorithm, which is the most improtant subtask in the high level synthesis. The proposed algorithm performs scheduling in consideration of resource sharing concept based on characteristics of conditionsla bransches in the intermediate data structure. CDFG (control data flow graph) generated by a VHDL analyzer. This algorithm constructs a conditon graph based on time frame of each operation using both the ASAP and the ALAP scheduling algorithm. The conditon priority is obtained from the condition graph constructed from each conditional brance. The determined condition priority implies the sequential order of transforming the CDFG with conditonal branches into the CDFG without conditional branches. To minimize resource cost, the CDFG with conditional branches are transformed into the CDFG without conditonal brancehs according to the condition priority. Considering the data dependency, the hardware constraints, and the data execution time constraints, each operation in the transformed CDFG is assigned ot control steps. Such assigning of unscheduled operations into contorl steps implies the performance of the scheduling in the consecutive movement of operations. The effectiveness of this algorithm is hsown by the experiment for the benchmark circuits.

In this paper we propose an efficient robust path delay fault test genration algorithm for detection of path delay faluts in combinational ligic circuits. In the proposed robust test genration approach, the testability measure is computed for all gates in the circuit under test and these computed values are used to genrate weighted random delay test vetors for detection of path delay faults. For genrated robust test vectors, we perform fault simulation on ISCAS '85 benchmark circuits using parallel pattern technqieus. The results indicate that the proposed test genration method not only increases the number of detected robust path delay faults but also reduces the time taen to genrate robust tests.