The radiation pattern of a rectangular-grid array antenna consisted of rectangular waveguides is represented by multiplication of its element and array factors. Calculated radiation patterns for excitation of TES110T mode inside the waveguides suffer from the blindness at a particular direction on E-plane. Numerical simulations show that the blindness can be removed by inserting dielectric plug inside the waveguides or covering dielectric sheath in front of the waveguides.

Tungsten silicied (WSix) has been widely used for interconnection line to improve the speed and reliability of devices. It is known that WSix formed by silane reduction has poor step coverage and poor adhesion. In this research, WSix by dichlorosilane reduction showed excellent adhesion in cellophane adhesive tape test, and improved step coverage by two times. The crystal structure of the as-deposited WSix film by silane reduction was transformed from the hexagonal to the tetragonal structure during annealing treatment, while that by dichlorosilane reduction kept the stable tetragonal structure. The fluorine concentration in the WSix film by dichlorosilane was lower than that by silane.

Dielectric thin film of N/O ($Si_{3]N_{4}/SiO_{2}$) for high density stacked dynamic-RAM cell was formed by LPCVD and oxidation(dry & pyrogenic oxidation methods) of the top 7nm $Si_{3]N_{4}$ film. The thickness, structure and composition of this film were measured by ellipsometer, high resolution TEM, AES and SIMS. The insulating characteristics(I-V characteristics) were investigated by HP 4145, and the characteristics of TDDB (Time Dependent Dielectric Breakdown) were evaluated by using CCST(Current Constant Stress Time) method. In this experiment, The optimum oxidation condition for preparation of good insulating and TDDB characteristics of N/O film was pyrogenic oxidation at 85$0^{\circ}C$ for 30 minutes. The leakage current was reduced from 400pA to 7.5pA when SiO$_{2}$ film with thickness of 2nm was formed on the top of $Si_{3]N_{4}$ film by the pyrogenic oxidation method.

Dielectric thin film of N/O (Si$_{3}N_[4}/SIO_{2}$) for high density stacked dynamic-RAM cell was formed by LPCVD and oxidation(Dry & pyrogenic oxidation methods) of the top Si$_{3}N_[4}$ film. The thickness, structure and composition of this film were measured by ellipsometer, high frequency C-V meter, high resolution TEM, AES, and SIMS. The thickness limit of Si$_{3}N_[4}$ film in making thin N/O structure layer was 7nm. In this experiment, the film with thinner than 7nm was not thick enough as oxygen diffusion barrier, and oxygen punched through the film and interfacial oxidation occurred at the phase boundary between Si$_{3}N_[4}$ and polycrystalline silicon electrode.

The Modified Multi-Quantum Well(MMQWAl) structures have been grown by Mental-Organic chemical Vapor Deposition(MOCVD) method and stripe type MMQW laser diodes have been investigated. In the case of GaAs/AlGaAs superlattice and quantum well growth by MOCVD, the periodicity, interface abruptess, Al compositional uniformity and layer thickness have been confirmed though the shallow angle lapping technique, double crystal x-ray diffractometry (DCXD) and photoluminescence (PL) measurement. stripe-type MMQW laser diodes have been fabricated using the process technology of photolithography, chemical etching, ohmic contact, back side removing and cleaving. As the result of the electrical and opticalmeasurement of these laser diodes, we have achieved the series resistance of $1[\Omega}~2{\Omega}$ by current-voltage measurements, the threshold current of 200-300mA by currnt-light measurements and the lasing wavelength of 8000-8400$\AA$ by lasing spectrum measurements.

본 논문에서는 다층유전체 구조를 갖는 VLSI interconnection line 에 대한 커페시턴스를 계산하기 위한 방법을 제안한다. 이 방법은 단일 유전체 구조에서 개발한 3차원 직접 적분방법을 확장한 것이다. 다층유전체에 의한 영향은 Green's function을 수정하는 대신에 경계조건을 추가함으로써 고려하였다. 여기서 사용한 경계조건은 line 표면에서는 전위에 대한 식을 사용하였고, 유전체 경계면ㅇ서는 전계에 대한 식을 사용하였다. 이 방법으로부터 얻어진 커패시턴스를 이용하여 다층유전체 구조에서의 interconnection line에 대한 RC 지연시간의 값을 구했다. 이때 사용한 interconnection 물질은 Al과 WSi-이다.

Because of a small bandgap energy, a high doping density, and a low operating temperature, the dark current in HgCdTe photodiode is almost composed of a tunneling current. The tunneling current is devided into an indirect tunneling current via traps and a band-to-band direct tunneling current. The indirect tunneling current dominates the dark current for a relatively high temperature and a low reverse bias and forward bias. For a low temperature and a high reverse bias the direct tunneling current dominates. In this paper, to verify the tunneling currents in HgCdTe photodiode, the new tunneling-recombination equation via trap is introduced and tunneling-recombination current is calculated. The new tunneling-recombination equation via trap have the same form as SRH (Shockley-Read-Hall) generation-recombination equation and the tunneling effect is included in recombination times in this equation. Chakrabory and Biswas's equation being introduced, band to band direct tunneling current are calculated. By using these equations, HgCdTe (mole fraction, 0.29 and 0.222) photodiodes are analyzed. Then the temperature dependence of the tunneling-recombination current via trap and band to band direct tunneling current are shown and it can be known what is dominant current according to the applied bias at athe special temperature.

In this paper, we introduce an integrated layout design system, SOLGER. Our system incorporates useful design tools : a powerful layout editor, a coherent access mechanism for large volumes of design data, an incremental design rule checker for hierarchical design environment, node extractor and electrical rule checker, a technology capture which is used for defining technology-specific information, and a procedural design environment for user customization. Also, we present a modified corner-stitching data structure which allows 45$^{\circ}$-angled bilateral edges. Users are provided with a multi-window design environment and a menu-driven interface. SOLGER is being used for VLSI designs practically.

The DSP silicon compiler consists of language compiler, module generator, placement tool, router, layout generation tools, and simulator. In this paper, The language compiler, the module generator, placement tool, and simulator were developed and provided for the system designer. The language compiler translates the designer's system description language into the intermediate form file. The intermediate form file expresses the interconnections and specifications of the cells in the cell library. The simulator was developed and provided for the behavioral verification of the DSP system. For its implementation, the event-driven technique and the C$^{++}$ task library was used. The module generator was developed for the layout of the verified DSP system, and generates the functional block to be used in the DSP chip. And then the placement tool determines the appropriate positions of the cells in the DSP chip. In this paper, the placement tool was implemented by Min-Cut and Simulated Annealing algorithm. The placement process can be controlled by the several conditions input by the system designer.

In this paper, the new timing optimization algorithm for combinational networks is proposed. First, we introduce the concept of P-path redundancy which is the extension of redundancy concept used in the testing of combinational networks. In this approach, the critical delay is minimized by removing the P-path redundant side inputs of the critical path, and more accurate timing optimization is possible by systematically considering the statically unsensitizable paths as well as the statically sensitizable paths. It's possible with all previous longest path based approaches that the critical delay of resulting network after timing optimization may be even increased. However, the proposed method guarantees to exclude such a possibility, and can be applied to optimize the timing of combinational networks in technology independent, and dependent phase.