The first thing in designing application-specific instruction set processor is having instruction set closely matching hardware characteristics. This instruction set design problem can be more complicated when cobined with implementation method selection problem of each instruction. Our processor model supports two kinds of instructions-primitive or special instructions. Primitive instructions are implemented using common multifunctional hardware such as ALU. Special instructions require a set of dedicated hardware, which actually functions as a coprocessor to the main processor. In this case, special instructions and primitive instructions can be executed independently. In this paper, we present novel algorithm for genrating special instructions for given application. Parallelism between special instructions and primitive instructions is also considered during the performance estimation stage of generated special instructions.

A signal line potential variation due to the delta-I noise was physically investigated in CMOS integrated circuits. An equivalent circuit for the noise analysis was presented. The signal line was modeled as segmented RC-lumped circuits with the ground noise. Then the equivalent circuit was mathematically analyzed. Therebvy a new signal line potential variation model due to the switching mosie was developed. Th emodel was verified with 0.35.mu.m CMOS deivce model parameters. The model has an excellent agreement with HSPICE simulation. Thus the proposed model can be dirctly employed in the industry to design the high-performance integrted circuit design as well as integrated circuit package design.

As the packing density of ICs in recent submicron IC design increases, interconnects gain importance. Because interconnects directly affect on two major components of circuit performance, power dissipation and operating speed, circuit engineers are concerned with the optimal design of interconnects and the aid tool to design them. When circuit models of interconnects are given (including geometry and material information), the analysis process for the given structure is not an easy task, but conversely, it is much more difficult to design an interconnect structure with given circuit characteristics. This paper focuses on the latter process that has not been foucsed on much till now due to the complexity of the problem, and prsents a design aid tool(DATOIS) to synthesize interconnects. this tool stroes the circuit performance parameters for normalized interconnect geometries, and has two oeprational modes:analysis mode and synthesis mode. In the analysis mode, circuit performance parameters are obtained by searching the internal database for a given geometry and interpolates results if necessary . In thesynthesis mode, when a given circuit performance parameter satisfies a set of geometry condition in the database, those geometry structures are printed out.

Memory management is one of the most important problems in implementing viterbi decoders. This paper introduces a novel traceback scheme for memory management of high-speed viterbi decoders. The new method balances the read and the write oeprations by inserting dummy write operations into the traceback process, resulting in simpler memory access schemes. It is suitable for VLSI implementation since it uses minimal memory requirements, it does not need global interconnections, and its address genration shceme for accessig memory contents is very simple.

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.

In this paper, we propose a synthesis algorithm for the design of low powe rcombinational circuits under area constraints. The proposed algorithm partitions a given circuit into several subcircuits such that only a selected subcircuit is activated at a time, hence reduce unnecessary signal transitions. Partitioning of a given circuit is performed through adaptive simulated annealing algorithm employing the cost function reflecting poer consumption under area constraints. Experimental reuslts for the MCNC benchmark circuits show that the proposed algorithm generates the circuits which consume less power by 61.1% and 51.1%, when compared to those generated by the sis 1.2 and the precomputation algorithm, respectively.

This paper is to develop an algorithm for the unlimited korean speech synthesis. We present the results controlled of prosodic factors with isolated words as aynthesis basis unit int he time domain. With a new pitch-synchronous and parametric speech synthesis mehtod in the time domain here we mainly present the results of controlled prosody factors such a spitch periods, energy envelops and durations and the evaluaton of synthetic speech qualities. In the case of synthesis, it is possible ot synthesize connected words by controlling of a continuous unified prosody that makes to improve the naturalities. In the results of experiment, it also has been to be improved uncontinuities of pitch and zeroing of energy in the junction parts of speech waveforms. Specially it has been to be possible to synthesize speeches with unlimitted durations and tones. So on it makes the noisiness and the clearness better by improving the degradation effects from the phase distortion due to the discontinuities in the waveform connection parts.

In this paper, a controller is designed for efficient controlling of video data with object-oriented feature. The need of controlling video data in an object unit is on the rise for the reason of rapidly growing demand for high-quality video services. We propose a programmable architecture with stack buffers which can minimize a scheduling overhead by having separate buffes for genral data and return addresses. The buffers are veyr useful for move and copy operations for multitasking and task switching. The controller offers extended instructions that process several data types including 32bit integrer type. Operation speed of the controller is from 77MHz to 44MHz.

This paper presents modular design techniques of multiple-valued logic functions about the function decomposition method and input variable management method. The function decomposition method takes avantage of the property of the column multiplicity in a single-column variable partitioning. Due to the increased number of identical modules, we can achieve a simpler circuit design by using a single T-gate, which can eliminate some of the control functions in the module libraty types. The input variable management method is to reduce the complexity of the input variables by proposing the look up table which assign input variables to a code. In this case as the number of sub-functions increase the code-length and the size of the code-assignment table grow. We identify some situations where shard input variables among sub-functions can be further reduced by a simplicication technique. According to the result of adapting this method to a function, we have demonstrated the superiority of the proposed methods which is bing decreased to about 12% of interconnection and about 16% of T-gate numbers compare with th eexisting for th enon-symmetric and irregular function realization.

In this paper, we suggest a new identification method for sugeno-type fuzzy model via new data clustering strategy. The suggested algorithm is much simpelr than the original identification strategy adopted in. The algorithm suggested in this paper is somewhat similar to that of [2] and [6], that is the algorithm suggested in this paper consists of two steps: coarse tuning and fine tuning. In this paper, double clustering strategy is proposed for coarse tunign. Finally, the resutls of computer simulation are given to demonstrate the validity of this algorithm.

In this paper, after we got to realized FDNN (fuzzy decision neural network) applied the quantization triangularity fuzzy function to DBNN(decision based neural network) of a hierarchical structure for image process, we could esign hardware of the realized FDNN. Also it is normalized the standard image and the input image as the same size. We are applied DWW algorithm which selected the closest value with finding similarity of an interval image by this distance to FDNN. So we could calulated in terms of distance to weight of pixel which composed two image and eliminated the nise of image, minimized the lost of information, obtained the optimal information. It is designed hardware of high speed weighted FDNN using COMPASS tool. Aslo, the total circuit is realized as gates of 61,000 and could show to superiority of FDNN using the simulation.