1V-2.7ns 32b self-timed parallel carry look-ahead adder with wave pipeline dclock control

웨이브 파이프라인 클럭 제어에 의한 1V-2.7ns 32비트 자체동기방식 병렬처리 덧셈기의 설계

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.