Journal of the Korean Institute of Telematics and Electronics C (전자공학회논문지C)
- Volume 35C Issue 7
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- Pages.46-58
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- 1998
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- 1226-5853(pISSN)
A partitioning-based synthesis algorithm for the design of low power combinational circuits under area constraints
면적 제약조건하의 저전력 조합회로 설계를 위한 분할 기반 합성 알고리즘
- Choi, Ick-Sung (Dept. of Electronic Engineering Sogang Univ.) ;
- Kim, Hyoung (Dept. of Computer Science Kyungmin Univ.) ;
- Hwang, Sun-Young (Dept. of Electronic Engineering Sogang Univ.)
- Published : 1998.07.01
Abstract
In this paper, we propose a synthesis algorithm for the design of low powe rcombinational circuits under area constraints. The proposed algorithm partitions a given circuit into several subcircuits such that only a selected subcircuit is activated at a time, hence reduce unnecessary signal transitions. Partitioning of a given circuit is performed through adaptive simulated annealing algorithm employing the cost function reflecting poer consumption under area constraints. Experimental reuslts for the MCNC benchmark circuits show that the proposed algorithm generates the circuits which consume less power by 61.1% and 51.1%, when compared to those generated by the sis 1.2 and the precomputation algorithm, respectively.
Keywords