According the difference of flex substrate, (reel tape), there are three kind assembly types of LCD driver IC is COG, TCP and COF, respectively. The TCP is the maturest in these types for stability of raw material supply and other specification. And TCP is the major assembly type of LCD driver IC and the huge demand from Taiwan's large TFT LCD panel house since this spring. But due to its package structure and the raw material applied in this package, there is some limitation in fine pitch application of this package type, (TCP). So, COF will be very potential in compact and portable application comparison with TCP in the future. There are three kinds assembly methods in COF, one is ACF by using the anisotropic conductive film to connect the copper lead of tape and gold bump of IC, another is eutectic bonding by using the thermo-pressure to joint the copper lead of tape and gold bump of IC, and last is NCP by using non-conductive paste to adhere the copper lead of tape and gold bump of IC. To have a global realization, this paper will briefly review the status of Taiwan's large TFT panel house, the internal driver IC design house, and the back-end assembly house in the beginning. The different material property of raw material, PI tape is also compared in the paper. The more detail of three kinds of COF assembly method will be described and compared in this paper.

$\Box$ LTCC/LTCC-M technologies are a cost-effective SOP technology $\Box$ LTCC/LTCC-M materials have good RF characteristics and the materials can be used as excellent substrates for high band width applications $\Box$ Reliability of LTCC/LTCC-M package or module can be greatly improved by embedded passive technology and CTE control of the substrates $\Box$ To expand the application area, more development is needed in realization of embedded passives with tight tolerance

The status of IC industry in Taiwan will be mentioned briefly in the first place. Focus will be mainly on the technology and business of packaging industry in Taiwan. The developments and accomplishments of packaging technology by either research institute or packaging industry will also be introduced. Introduction.

Root cause -Thermal expansion coefficient mismatch -Tape warpage -Initial die crack (die roughness) Guideline for failure prevention -Optimized tape/Substrate design for minimizing the warpage -Fine surface of die backside Root cause -Thermal expansion coefficient mismatch - Repetitive bending of a signal trace during TC cycle - Solder mask damage Guideline for failure prevention - Increase of trace width - Don't make signal trace passing the die edge - Proper material selection with thick substrate core Root cause -Thermal expansion coefficient mismatch -Creep deformation of solder joint(shear/normal) -Material degradation Guideline for failure Prevention -Increase of solder ball size -Proper selection of the PCB/Substrate thickness -Optimal design of the ball array -Solder mask opening type : NSMD -In some case, LGA type is better

Reliability.The reliability strongly depended on the CTE of underfill resin..The fractured portion was identical with the maximum plastic equivalent strain..1 % or less value of the maximum plastic equivalent strain certified more than 1000 cycle of TCT life. UFB.Bonding accuracy was confirmed within2$2{\mu}{\textrm}{m}$..The fundamental bondability of UFB was confirmed with no damage around aluminum pads. Some dislocations and vacancies were observed at the interface, however, the atomic level bonding was confirmed. CBB.Dry process was applied to UBM removal.

Using eutectic In-Ag and Bi-Sn solder materials, we developed the COG technique having a minimum pitch of 50 ${\mu}{\textrm}{m}$. The maximum temperature in this process is $160^{\circ}C$. We fabricated spherical and uniform solder bumps by controlling the microstructure of Bi-Sn solder bumps. The contact resistances of Bi-Sn solder joints were 19 m$\Omega$ at $80{\mu}{\textrm}{m}$ pitch and 60 m$\Omega$ at $80{\mu}{\textrm}{m}$ pitch, respectively. These values are much lower than the contact resistance of the conventional ACF bonding. The contact resistances of the solder joint are almost the same before and after the underfill process. The contact resistance of the underfilled Bi-Sn solder joint did not change even after reliability test.

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.