In this paper, the difference between call processing routing of general purpose ESS and that of special purpose ESS, such a TDX-ACD, was specified by analyzing the call processing capacity of special purpose ESS. Then the load sharing method was proposed in orde to reduce the overload condition in specific processors. Finally, measirement value was illustrated nad compared with simulation value.

In this paper, a design method of a robust adaptive regulator with feedfoward path based on the explicit criterion minimization is proposed. The convergence speed of parameter estimation is improved by using the stochastic Newton minimization method in the criterion minimization algorithm, and sensitivity derivatives are used in the regulator calculation for improving the robustness of the control system. Trh proposed adaptive regulator is applied to the stable minimum-phase and nonminimum-phase system, the results are shown that control performance and disturbance compensation ability of the regulator are improved. And the choosing method of input penalty is proposed.

This paper proposes the control unit of a 32-bit high-performance RISC type microprocessor. This control unit controls the whole data path of target processor and on chip instruction/data caches in 4-stage pipelined scheme. For the improvement of speed, large parts of data path and control unit are designed by domino-CMOS and hard-wired circuit technology. First, in this paper, target processor's instruction set and data path are defined, and next, all signals needed to control the data path are analyzed. The decoder of control unit and clock generated logic block are implemented in DCAL(Dynamic CMOS Array Logic) with modified clock scheme for the purpose of speed up and supporting RISC processor's pipelined architecture efficiently.

This paper proposes a program counter unit(PCU) on the pipelined architecture of RISC (Reduced Instruction Set Computer) type high performance processors, PCU is used for supplying instruction addresses to memory units(Instruction Cache) efficiently. A RISC processor's PCU has to compute the instruction address within required intervals continnously. So, using the method of self-generated incrementor, is more efficient than the conventional one's using ALU or private adder. The proposed PCU is designed to have the fast +4(Byte Address) operation incrementor that has no carry propagation delay. Design specifications are taken by analyzing the whole data path operation of target processor's default and exceptional mode instructions. CMOS and wired logic circuit technologic are used in PCU for the fast operation which has small layout area and power dissipation. The schematic capture and logic, timing simulation of proposed PCU are performed on Apollo W/S using Mentor Graphics CAD tooks.

We proposed a neural network energy function for the optimal graph partitioning and its optimization method using Boltzmann Machine. We composed a Boltzmann Machine with the proposed neural network energy function, and the simulation results show that we can obtain an optimal solution with the energy function parameters of A=50, B=5, c=14 and D=10, at the Boltzmann Machine parameters of To=80 and \ulcorner0.07 for a 6-node 3-partition problem. As a result, the proposed energy function and optimization parameters are proved to be feasible for the optimal graph partitioning.

In this paper, under pinch-off conditions, the gate-drain breakdown voltage characteristics of GaAs Power MESFET's as a function of device parameters such as channel thickness, doping concentration, gate length etc. are analyzed. Using the Green's function, the gate ionic charge induced by the depleted channel ionic charge is calculated. The impact ionization integral by avalanche multiplication between gate and drain is used to investigate breakdown phenomena. Especially, the localized excess surface charge effect as well as the uniform surface charge effect on breakdown voltage is considered.

The approximations of charge relationships at normally doped semiconductor interfaces were qualitatively derived basis on electrical neutrality conditions. Effects of ion adsorptions, activation processes, interfacial structures, rectifying phenomena, and effects of surface potential barriers at the p- and n-Si/CsNO3 aqueous electrolytes, and the p-Si/(1HF:3HNO3:6H2O) electrolyte solutions were investigated using a cyclic voltammetric method. The space charge acts the most important role for the pn junction structures, the rectifying phenomena, and the activation processes. The Current-Voltage (I-V) characteristics curves significantly depend on developing of the Helmholtz double layers and charging of the show surface states during the activation processes. A linear Current-Voltage characteristics region was observed at the p-Si/(1HF:3HNO3: 6H2O) electrolyte solution interface.

Mathematical modeling equations of a parallel plate type reactor were obtained in the PECVD process in preparing hydrogenated amorphous silicon. Velocity profiles, temperature profiles and concentration profiles in the reactor were calculated from the model. The theoretical approach was attempted to obtain the deposition rate and film uniformity at different operating conditions by calculating RF discharge parameters and establishing the reaction mechanisms of a-Si:H thin film. The modelling equations are solved by a finite difference method with control volume balance. The mean electrom energy in discharge was applied to model simulation parameter. The magnitudes of the predicted deposition rate are in good aggrement with those of experiment. The results of computer simulation shows that uniform deposition profiles can.

In this paper a new test generation method for Domino CMOS logic circuits is proposed. Because the stuck-at type fault is not adequate for Domino CMOS circuits the stuck-open fault, stuck-on fault and bridging fault are considered as fault models. It is shown that the test generation problem of Domino CMOS circuits results in functional block test generation problem. Test set is generated by using the logic minimizer which is a part of logic design system. An algorithm for reduction of test set is described. The proposed test method can be easily applied to various figures of circuits and make it easy to construct automatic test generator in design system. The proposed algorithms are programed and their efficiency is confirmed by examples.