• Transactions on Electrical and Electronic Materials
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• 제4권2호
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• pp.15-19
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• 2003

In this paper, the new dual trench gate Emitter Switched Thyristor (DTG-EST) is proposed for improving snap-back effect which leads to a lot of serious problems of device applications. Also the parasitic thyristor that is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and 35A/$\textrm{cm}^2$, respectively. But the proposed DTG-EST exhibits snap-back with the anode voltage and current density 0.96V and 100A/$\textrm{cm}^2$, respectively.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.838-843
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• 2002

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

• 한국전기전자재료학회논문지
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• 제23권3호
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• pp.183-189
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• 2010

In this paper, the trench gate emitter switched thyristor(EST) withl trench gate electrode is proposed for improving snap-back effect which leads to a lot of problems in device applications. The parasitic thyristor which is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The dual trench gate allows homogenous current distribution in the EST and preserves the unique feature of the gate controlled current saturation of the thyristor current. The characteristics of the 1700 V forward blocking EST obtained from two-dimensional numerical simulations (MEDICI) is described and compared with that of a conventional EST. we carried out layout, design and process of EST devices.

• 한국전기전자재료학회논문지
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• 제25권4호
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• pp.270-275
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• 2012

Power MOSFET(metal oxide silicon field effect transistor) operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. But on-resistance characteristics depending on the increasing breakdown voltage spikes is a problem. So 600 V planar power MOSFET compare to 1/3 low on-resistance characteristics of super junction MOSFET structure. In this paper design to 600 V planar MOSFET and super junction MOSFET, then improvement of comparative analysis breakdown voltage and resistance characteristics. As a result, super junction MOSFET improve on about 40% on-state voltage drop performance than planar MOSFET.

• Transactions on Electrical and Electronic Materials
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• 제3권4호
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• pp.5-9
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• 2002

Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. Especially, to achieve the higher density and greater performance, shallow trench isolation (STI)-CMP process has been attracted attention for multilevel interconnection as an essential isolation technology. Also, it was possible to apply the direct STI-CMP process without reverse moat etch step using high selectivity slurry (HSS). In this work, we determined the process margin with optimized process conditions to apply HSS STI-CMP process. Then, we evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions. The wafer-to-wafer thickness variation and day-by-day reproducibility of STI-CMP process after repeatable tests were investigated. Our experimental results show, quite acceptable and reproducible CMP results with a wafer-to-wafer thickness variation within 400$\AA$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 기술교육전문연구회
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• pp.27-30
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• 2003

In this paper, the new dual trench gate Emitter Switched Thyristor (DTG-EST) is proposed for improving snap-back effect which leads to a lot of serious problems of device applications. And the parasitic thyristor that is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and $35A/cm^2$, respectively. But the proposed DTG-EST exhibits snap-back with the anode voltage and current density 0.96V and $100A/cm^2$, respectively.

• KIEE International Transactions on Electrophysics and Applications
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• 제3C권1호
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• pp.28-32
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• 2003

In this paper, we have studied the in-situ end point detection (EPD) for direct chemical mechanical polishing (CMP) of shallow trench isolation (STI) structures without the reverse moat etch process. In this case, we applied a high selectivity $1n (HSS) that improves the silicon oxide removal rate and maximizes oxide to nitride selectivity Quite reproducible EPD results were obtained, and the wafer-to-wafer thickness variation was significantly reduced compared with the conventional predetermined polishing time method without EPD. Therefore, it is possible to achieve a global planarization without the complicated reverse moat etch process. As a result, the STI-CMP process can be simplified and improved using the new EPD method.

• 대한전기학회논문지
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• 제45권2호
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• pp.230-234
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• 1996

A new trenched Hybrid Schottky INjection Field Effect Transistor (HSINFET) is proposed and verified by 2-D semiconductor device simulation. The feature of the proposed structure is that the hybrid Schottky injector is implemented at the trench sidewall and p-n junction injector at the upper sidewall and bottom of a trench. Two-dimensional simulation has been performed to compare the new HSINFET with the SINFET, conventional HSINFET and lateral insulated gate bipolar transistor(LIGBT). The numerical results shows that the current handling capability of the proposed HSINFET is significantly increased without sacrificing turn-off characteristics. The proposed HSINFET exhibits higher latch-up current density and much faster switching speed than the lateral IGBT. The forward voltage drop of the proposed HSINFET is 0.4 V lower than that of the conventional HSINFET and the turn-off time of the trenched HSINFET is much smaller than that of LIGBT.

• 대한전기학회논문지
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• 제45권2호
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• pp.249-255
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• 1996

A self-aligned latch-up suppressed IGBT has been proposed and the process method and the device characteristics of the IGBT have been verified by numerical simulation. As the source is laterally diffused through the sidewall of the trench in the middle of the body, the size of the source is small and the doping concentration of the source is lower than that of the p++ body and the emitter efficiency of the parasitic npn transistor is low so that latch-up may be suppressed. No additional mask steps for p++ region, source, and source contact are required so that small sized body can be obtained Latch-u current density higher than 10000 A/cm$^{2}$ have been achieved by adjusting the process conditions.

• 한국전기전자재료학회논문지
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• 제27권8호
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• pp.501-504
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• 2014

This paper was developed and described core-process to implement low on resistance which was the most important characteristics of SJ (super junction) MOSFET. Firstly, using process-simulation, SJ MOSFET optimal structure was set and developed its process flow chart by repeated simulation. Following process flow, gate level process was performed. And source and drain level process was similar to genral planar MOSFET, so the process was the same as the general planar MOSFET. And then to develop deep trench process which was main process of the whole process, after finishing photo mask process, we developed deep trench process. We expected that developed process was necessary to develop SJ MOSFET for automobile semiconductor.