• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.1
• /
• pp.156-161
• /
• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.8
• /
• pp.71-77
• /
• 1992

According to increasing the doping concentration in p-n junction, a tunneling current through trap as well as SRH(Shockley-Read-Hall) generation-recombination current in depletion region occurs. It is the tunneling current that is a dominant current at the forward bias. In this paper, the new tunneling-recombination equation is derived. The thermal generation-recombination current and tunneling current though trap can be easily calculated at the same time because this equation has the same form as the SRH generation-recombination equation. For the validity of this equation, 2 kind of samples are simulated. The one is $n^{+}$-p junction device fabricated with MCT(Mercury Cadmium Telluride, mole fraction=0.29), the other Si n$^{+}-p^{+}$ junction. From the results for MCT $n^{+}$-p junction device and comparing the simulated and expermental I-V characteristics for Si n$^{+}-p^{+}$ junction, it is shown that this equation is a good description for tunneling through trap and thermal generation-recombination current calculation.

• Transactions on Electrical and Electronic Materials
• /
• v.14 no.5
• /
• pp.250-253
• /
• 2013

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of $N_2$ ion implantation ($N_2$ I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage ($V_{\tau}$) of 0.13 V, and a higher $g_{m.max}$ of 18.6 ${\mu}A/V$ and mobility of 27.02 $cm^2/Vs$ than the conventional and $N_2$ I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and $N_2$ I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.2
• /
• pp.53-63
• /
• 1993

Device degradations by the Fowler-Nordheim tunneling have been studide. The changes of device characteristics such as the threshold voltage, subthreshold slope, I-.or. curves have been measured after bidirectionally stressing n-channel MOSFET's and p-channel MOSFET's. Also the interface states have been directly measured by the charge pumping methodIt is shown that the change of interface states is determined by the number of hole carriers tunneling the gate oxide and electrons which are trapped in the gate oxide. Also, in this paper, we propose a model for device lifetime limited by the increase of interface states.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.5
• /
• pp.955-960
• /
• 2007

In this paper, the deviation of tunneling current for gate voltage has been investigated in double gate MOSFET developed to decrease the short channel effects. In device scaled to nano units, the tunneling current is very important current factor and rapidly increases,compared with thermionic emission current according to device size scaled down. We consider the change of tunneling current according to gate voltage in this study. The potential distribution is derived to observe the change of tunneling current according to gate voltage, and the deviation of off-current is derived from the relation of potential distribution and tunneling probability. The derived current is compared with the termionic emission current, and the relation of effective gate voltage to decrease tunneling current is obtained.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.1
• /
• pp.17-21
• /
• 2009

The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated for nonvolatile memory device applications. The band structure of band-gap engineered tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with the conventional tunneling $SiO_2$ barrier. The band-gap engineered tunneling barriers composed of thin $SiO_2$ and $Si_3N_4$ layers showed a lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.

• Journal of the Korean Vacuum Society
• /
• v.20 no.1
• /
• pp.57-62
• /
• 2011

We have studied the electrical and magnetic transport properties of tunneling device with FePt magnetic quantum dots. The FePt nanoparticles with a diameter of 8~15 nm were embedded in a $SiO_2$ layer through thermal annealing process at temperature of $800^{\circ}C$ in $N_2$ gas ambient. The electrical properties of the tunneling device were characterized by current-voltage (I-V) measurements under the perpendicular magnetic fields at various temperatures. The nonlinear I-V curves appeared at 20 K, and then it was explained as a conductance blockade by the electron hopping model and tunneling effect through the quantum dots. It was measured also that the negative magneto-resistance ratio increased about 26.2% as increasing external magnetic field up to 9,000 G without regard for an applied electric voltage.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.42 no.3
• /
• pp.585-594
• /
• 2017

Wireless Docking system can provide enhanced convenience to user experience of handheld device such as smart phone by using previously deployed peripheral devises such as monitor and keyboard. In this environment, user can easily use the handheld device with variable peripheral devices at any docking system place. This system would be composed of peripherals except host computing device contrarily to previous desktop and laptop environment. For this system, Wi-Fi Alliance has been developing standard technology based on Wi-Fi Direct(Wi-Fi Peer-to-Peer Technical Specifications v1.2, 2010) technology. However, this system can make a problem which may lead to complex connectivity on handheld device due to non-compatible communication interface. To address given problem, we designed a new method of Bluetooth tunneling technology via previous Wi-Fi Direct communication, and evaluated it with experiment results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.189-190
• /
• 2008

The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated. The band structure of stacked tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with that of the conventional tunneling barrier. The band-gap engineered tunneling barriers show the lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2019.05a
• /
• pp.475-476
• /
• 2019

L-shaped tunneling field-effect-transistor (LTFET) is considered a superior device over conventional TFETs. However, experimentally demonstrated LTFET demonstrated poor subthreshold characteristics which was attributed to trap-assisted-tunneling (TAT) caused by presence of trap states. In this paper, TAT mechanism in the experimentally demonstrated LTFET is investigated with the help of band diagram and TAT recombination rate (GTAT).