• ETRI Journal
• /
• 제38권2호
• /
• pp.272-279
• /
• 2016

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

• 전자공학회논문지A
• /
• 제28A권10호
• /
• pp.821-829
• /
• 1991

In this paper, a BICMOS technology that has CMOS devices for digital application and bipolar devices for high voltage (80V) analog applications is presented. Basic concept to design BICMOS device is simple process technology without making too many performance trade-offs. The base line process is poly gate p-well CMOS process and three additional masking steps are added to improve bipolar characteristics. The key ingredients of bipolar integration are n+ buried layer process, up/down isolation process and p-well base process. The bipolar base region is formed simultaneously with the region of CMOS p-well area to reduce mask and heat cycle steps. As a result, hFE value of NPN bipolar transistor is 100-150(Ic=1mA). Collector resistance value is 138 ohm in case of bent type collector structure. Breakdown voltage of BVebo, BVcbo and BVceo are 21V, 115V and78V respectively. Threshold voltage is ${\pm}$1.0V for NMOS and PMOS transistor. Breakdown voltage of NMOS and PMOS transistor is obtained 22V and 19V respectively. 41 stage CMOS ring oscillator has 0.8ns delay time.

• 센서학회지
• /
• 제17권1호
• /
• pp.41-52
• /
• 2008

In this paper, a circuit analysis of the complementary CMOS active pixel and readout circuit is carried out. Complementary pixel structure which is different from conventional 3TR APS structure is consist of photo diode, reset PMOS, several NMOSs and PMOSs sets for complementary signals. Photo diode is modelled with Medici device program. HSPICE was used to analyze the variation of the signal feature depending on light intensity using $0.5{\mu}M$ standard CMOS process. Simulation results show that the output signal range is from 0.8 V to 4.5 V. This signal range increased 135 % output dynamic range compared to conventional 3TR pixel in the condition of 5 V power supply.

• 한국정보통신학회논문지
• /
• 제16권3호
• /
• pp.565-570
• /
• 2012

본 논문은 LTE-Advanced 시스템을 위한 멀티채널을 선택할 수 있는 저역통과 필터를 제안한다. 제안하는 저역통과 필터는 5 MHz, 10 MHz, 그리고 40 MHz의 3가지 모드의 차단주파수를 제공하며 Active-RC 5차 Chebyshev 구조로 설계되었다. 저전력을 확보하면서 40 MHz의 높은 차단 주파수를 확보하기 위해서 부성 저항을 가지는 PMOS Cross-Connection Load를 사용한 연산증폭기를 필터에 적용하였다. 더불어 공정, 전압, 그리고 온도에 의한 각각의 차단주파수 변화에 대응할 수 있도록 각각 3-bit 제어 가능한 튜닝회로를 추가하였다. 제안하는 필터는 0.13-${\mu}m$ CMOS 공정을 사용하여 설계하였으며 1.2 V 전압에서 총 20.9 mW 전력을 소모한다.

• 한국전기전자재료학회논문지
• /
• 제18권2호
• /
• pp.120-124
• /
• 2005

In this work, MOS capacitors were used to study the electrical properties of Mo gate electrode deposited on ZrO$_2$. The workfunctions of Mo gate extracted from C-V curves were appropriate for PMOS. Thermal stability of Mo metal was investigated by analyzing the variations of workfunction and EOT(effective oxide thickness) after 600, 700, and 800 $^{\circ}C$ RTA(rapid thermal annealing). It was found that Mo gate was stable up to 800 $^{\circ}C$ with underlying ZrO$_2$. The resistivities of Mo were 35$\mu$Ω$.$cm∼ 75$\mu$Ω$.$cm. These values are lower than those of heavily doped polysilicon. Based on these measurements, it can be concluded that Mo metal gate with ZrO$_2$ gate insulator is an excellent gate material for PMOS.

• Journal of electromagnetic engineering and science
• /
• 제14권2호
• /
• pp.68-73
• /
• 2014

A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a $0.18-{\mu}m$ silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance ($C_{gs}$) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improved AM-PM. The linearizer is used at the gate of the driver-stage instead of main-stage transistor, thereby avoiding excessive capacitance loading while compensating the AM-PM distortions of both stages. The fabricated 836.5 MHz linear PA module shows an adjacent channel leakage ratio better than -40 dBc up to the rated linear output power of 27.1 dBm, and power-added efficiency of 45.6% at 27.1 dBm without digital pre-distortion.

• 정보처리학회논문지A
• /
• 제15A권2호
• /
• pp.69-74
• /
• 2008

본 논문은 MOS 전류모드 논리회로 (MOS current-mode logic circuit)의 누설전류를 감소시키기 위해 슬립 트랜지스터 (sleep-transistor) 트랜지스터를 이용하여 저 전력 MOS 전류모드 논리회로를 구현하는 새로운 구조를 제안하였다. 슬립 트랜지스터는 누설전류를 최소화하기 위해 고 문턱전압 PMOS 트랜지스터 (high-threshold voltage PMOS transistor)를 사용하였다. $16\;{\times}\;16$ 비트 병렬 곱셈기를 제안한 구조에 적용하여 제안한 구조의 타당성을 입증하였다. 이 회로는 기존 MOS 전류모드 논리회로 구조에 비해 대기전력소모가 1/50으로 감소하였다. 이 회로는 삼성 $0.35\;{\mu}m$ 표준 CMOS 공정을 이용하여 설계하였으며, HSPICE를 이용하여 검증하였다.

• ETRI Journal
• /
• 제35권4호
• /
• pp.594-602
• /
• 2013

This paper proposes printed organic one-time programmable read-only memory (PROM). The organic PROM cell consists of a capacitor and an organic p-type metal-oxide semiconductor (PMOS) transistor. Initially, all organic PROM cells with unbroken capacitors store "0." Some organic PROM cells are programmed to "1" by electrically breaking each capacitor with a high voltage. After the capacitor breaking, the current flowing through the PROM cell significantly increases. The memory data is read out by sensing the current in the PROM cell. 16-bit organic PROM cell arrays are fabricated with the printed organic PMOS transistor and capacitor process. The organic PROM cells are programmed with -50 V, and they are read out with -20 V. The area of the 16-bit organic PROM array is 70.6 $mm^2$.

• 한국위성정보통신학회논문지
• /
• 제9권4호
• /
• pp.63-68
• /
• 2014

PPS 구조를 갖는 N형 실리콘 제어 정류기 소자에서 부분웰 구조가 정전기 보호 성능에 미치는 영향을 고찰하였다. 종래의 NSCR 표준소자는 온-상태 저항, 스냅백 홀딩 전압 및 열적 브레이크다운 전압이 너무 낮아 정전기 보호소자의 필요조건을 만족시키지 못해 적용이 어려웠으나, 본 연구에서 제안하는 부분웰 구조를 갖도록 변형 설계된 NSCR-PPS 소자는 안정한 정전기보호 성능을 나타내어 고전압 동작용 마이크로 칩의 정전기보호 소자로 적용 가능함을 확인하였다.

• 한국통신학회논문지
• /
• 제25권10A호
• /
• pp.1582-1589
• /
• 2000

본 논문에서는 GHz 대역에서 동작하며 소모전력이 적은 동적 D-flipflop을 제안한다. 제안하는 D-flipflop은 두 가지 측면의 장점을 제공한다. 첫째, 클럭 입력을 갖는 PMOS 트랜지스터의 개수를 줄여 기존회로와 동일한 면적하에서도 고속 동작을 할 수 있다. 둘째, 클럭 업력을 갖는 NMOS 트랜지스터 공유에 의하여 glitch를 줄이고 소모전력을 낮출 수 있다. 제안하는 D-flipflop의 성능 비교를 위하여 기존회로와 동일한 면적의 레이아웃 회로에서 소모전력 및 최대동작주파수의 측정실험을 한다. 제안하는 회로의 응용 예로 고속 prescaler에서 동일한 방법의 특성실험을 한다. 성능분석결과 기존 회로에 비하여 동작속도와 전력소모 측면에서 우수한 성능을 나타냄을 확인하였다.