Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 28A Issue 10
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- Pages.821-829
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- 1991
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- 1016-135X(pISSN)
A Study on the 80V BICMOS Device Fabrication Technology
80V BICMOS 소자의 공정개발에 관한 연구
- Park, Chi-Sun (Dept. of Elec. Eng., Ajou Univ.) ;
- Cha, Seung-Ik (Dept. of Elec. Eng., Ajou Univ.) ;
- Choi, Yearn-Ik (Dept. of Elec. Eng., Ajou Univ.) ;
- Jung, Won-Young (Goldstar Electron R&D Center) ;
- Park, Yong (Goldstar Electron R&D Center)
- Published : 1991.10.01
Abstract
In this paper, a BICMOS technology that has CMOS devices for digital application and bipolar devices for high voltage (80V) analog applications is presented. Basic concept to design BICMOS device is simple process technology without making too many performance trade-offs. The base line process is poly gate p-well CMOS process and three additional masking steps are added to improve bipolar characteristics. The key ingredients of bipolar integration are n+ buried layer process, up/down isolation process and p-well base process. The bipolar base region is formed simultaneously with the region of CMOS p-well area to reduce mask and heat cycle steps. As a result, hFE value of NPN bipolar transistor is 100-150(Ic=1mA). Collector resistance value is 138 ohm in case of bent type collector structure. Breakdown voltage of BVebo, BVcbo and BVceo are 21V, 115V and78V respectively. Threshold voltage is
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