• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.59 no.4
• /
• pp.401-404
• /
• 2010

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.6
• /
• pp.742-750
• /
• 2018

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.1
• /
• pp.1-6
• /
• 2002

The hot carried degradation in a metal oxide semiconductor device has been one of the most serious concerns for MOS-ULSI. In this paper, three types of LDD(lightly doped drain) structure for suppression of hot carried degradation, such as decreasing of performance due to spacer-induced degradation and increase of series resistance will be investigated. in this study, LDD-nMOSFETs used had three different drain structure, (1) conventional surface type LDD(SL), (2) Buried type LDD(BL), (3) Surface implantation type LDD(SI). As experimental results, the surface implantation the LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structures.

• The Journal of the Acoustical Society of Korea
• /
• v.20 no.7
• /
• pp.37-46
• /
• 2001

This paper proposes a new noise suppression method using the Wavelet transform analysis. The noise suppressor using the Wavelet transform shows the more effective advantages in a babble noise than one using the short-time Fourier transform. We designed a new channel structure based on spectral subtraction of Wavelet transform coefficients and used the Wavelet mask pattern with more higher time resolution in high frequency. It showed a good adaptation capability for babble noise with a non-stationary property. To evaluate the performance of proposed noise canceller, the informal subjective listening tests (Mos tests) were performed in background noise environments (car noise, street noise, babble noise) of mobile communication. The proposed noise suppression algorithm showed about MOS 0.2 performance improvements than the suppression algorithm of EVRC in informal listening tests. The noise reduction by the proposed method was shown in spectrogram of speech signal.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.1
• /
• pp.1-11
• /
• 2002

In this paper, new simple method for the calculation of depletion region under complex geometry and general purpose numerical simulator that could handle this were developed and applied in the analysis of SCM with nanoscale tip, which is a promising tool for high resolution dopant profiling. Our simple depletion region seeking algorithm alternatively switches material of elements to align ionized element boundary with contour of zero potential. To prove the validity of our method we examined whether our results satisfy the definition of depletion region and compared those with known values of un junction and MOS structure. By modeling of capacitance based on the shape of depletion region and potential distribution, we could calculate the CV curve and dC/dV curve between silicon substrate and nanoscale SCM tip.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.10
• /
• pp.1-6
• /
• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

• Journal of the Korean Society of Industry Convergence
• /
• v.5 no.1
• /
• pp.39-43
• /
• 2002

In present much CMOS devices used in VLSI circuit and Logic circuit. With increasing a number of device in VLSI, the confidence becomes more serious. This paper describe the mechanism of breakdown on CMOS, especially n-MOS, based on Hydro Dynamic model with device self-heating. Additionally, illustrate the CMOS latch-up characteristics on simplified device structure on this paper.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.48 no.9
• /
• pp.605-610
• /
• 1999

An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with a recessed source structure is proposed to improve the on-resistance and the breakdown voltage. The recessed source structure can decrease the on-resistance by reducing the path of electron current, also increase the breakdown voltage by extending the effective length of gate field plate. Simulation results by TSUPREM4 and MEDICI have shown that the on-resistance of the LDMOS with a recessed source was 26% lower than conventional LDMOS. The breakdown voltage of proposed device was found to be 45V while that of conventional device was 36.5 V. At the same breakdown voltage of 36.5V, the on-resistance of the LDMOS with a recessed source was 41% lower than that of conventional structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.30 no.9
• /
• pp.589-595
• /
• 2017

MOS-FET structured gas sensors were manufactured using MWCNTs for application as NOx gas sensors. As the gas sensors need to be heated to facilitate desorption of the gas molecules, heat dispersion plays a key role in boosting the degree of uniformity of molecular desorption. We report the desorption of gas molecules from the sensor at $150^{\circ}C$ for different sensor electrode gaps (30, 60, and $90{\mu}m$). The COMSOL analysis program was used to verify the process of heat dispersion. For heat analysis, structure of FET gas sensor modeling was proceeded. In addition, a property value of the material was used for two-dimensional modeling. To ascertain the degree of heat dispersion by FEM, the governing equations were presented as partial differential equations. The heat analysis revealed that although a large electrode gap is advantageous for effective gas adsorption, consideration of the heat dispersion gradient indicated that the optimal electrode gap for the sensor is $60{\mu}m$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.10
• /
• pp.889-895
• /
• 2008

This paper presents a comprehensive mathematical analysis and simulation of trench IGBT with the help of PIN-PNP combinational model. Since trench IGBT is characteristically influenced by PIN diode, it may be almost impossible to analyze the trench IGBT using PNP-MOS modeling methods, even PIN-MOS techniques which neglect the hole current components coming into p-base region. A new PIN-PNP complementary cooperational model is developed in order to make up the drawbacks of existing models. It would allow us to make qualitative analysis as well as simulation about switching and on-state characteristics of 1,700 V trench IGBT. Moreover, if we improve the PIN diode effects through the optimization of trench structure, trench IGBT is expected to be one of the most promising devices in the not only high-voltage but also high speed switching device field.