The Journal of Korea Institute of Information, Electronics, and Communication Technology (한국정보전자통신기술학회논문지)

Korea Information Electronic Communication Technology (한국정보전자통신기술학회)
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Design of Zero-Layer FTP Memory IP

PMIC용 Zero Layer FTP Memory IP 설계

  • Ha, Yoongyu (Department of Electronic Engineering, Changwon National University) ;
  • Jin, Hongzhou (Department of Electronic Engineering, Changwon National University) ;
  • Ha, Panbong (Department of Electronic Engineering, Changwon National University) ;
  • Kim, Younghee (Department of Electronic Engineering, Changwon National University)
  • Received : 2018.12.21
  • Accepted : 2018.12.25
  • Published : 2018.12.29
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Abstract

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

본 논문에서는 $0.13{\mu}m$ BCD 공정 기반에서 5V MOS 소자만 사용하여 zero layer FTP 셀이 가능하도록 하기 위해 tunnel oxide 두께를 기존의 $82{\AA}$에서 5V MOS 소자의 gate oxide 두께인 $125{\AA}$을 그대로 사용하였고, 기존의 DNW은 BCD 공정에서 default로 사용하는 HDNW layer를 사용하였다. 그래서 제안된 zero layer FTP 셀은 tunnel oxide와 DNW 마스크의 추가가 필요 없도록 하였다. 그리고 메모리 IP 설계 관점에서는 designer memory 영역과 user memory 영역으로 나누는 dual memory 구조 대신 PMIC 칩의 아날로그 회로의 트리밍에만 사용하는 single memory 구조를 사용하였다. 또한 BGR(Bandgap Reference Voltage) 발생회로의 start-up 회로는 1.8V~5.5V의 전압 영역에서 동작하도록 설계하였다. 한편 64비트 FTP 메모리 IP가 power-on 되면 internal reset 신호에 의해 initial read data를 00H를 유지하도록 설계하였다. $0.13{\mu}m$ Magnachip 반도체 BCD 공정을 이용하여 설계된 64비트 FTP IP의 레이아웃 사이즈는 $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$)이다.

Keywords

JBJTBH_2018_v11n6_742_f0001.png 이미지

그림 1. FTP cell (a) 회로도 (b) 공정단면도. Fig. 1. FTP cell: (a) circuit and (b) process cross-sectional view.

JBJTBH_2018_v11n6_742_f0002.png 이미지

그림 2. 0.18㎛ BCD 공정으로 제작된 FTP 셀의 program voltage에 대한 program VT 와 erase VT 측정 결과. Fig. 2. Results of program VT and erase VT measurements with respect to program voltage for fabricated FTP cells based on the 0.18μm BCD process.

JBJTBH_2018_v11n6_742_f0003.png 이미지

그림 3. 설계된 64비트 FTP 메모리 IP의 블록도. Fig. 3. Block diagram of the designed 64-bit FTP memory IP.

JBJTBH_2018_v11n6_742_f0004.png 이미지

그림 4. BGR 회로도[9-10]. Fig. 4. BGR circuits: (a) concept circuit and (b) implemented circuit.

JBJTBH_2018_v11n6_742_f0005.png 이미지

그림 5. Start-up 회로. Fig. 5 Start-up circuits: (a) conventional circuit and (b) proposed circuit.

JBJTBH_2018_v11n6_742_f0006.png 이미지

그림 6. Sense amplifier 회로도 (a) OTP IP에 사용된 회로 (b) 제안된 회로. Fig. 6. Sense amplifier circuits: (a) circuit used in the OTP IP and (b) proposed circuit.

JBJTBH_2018_v11n6_742_f0007.png 이미지

그림 7. 설계된 64비트 FTP IP의 레이아웃 사진. Fig. 7. Layout image of the designed 64-bit FTP IP.

JBJTBH_2018_v11n6_742_f0008.png 이미지

그림 8. BGR 모의실험 결과 (a) 온도 변화에 대한 VREF 곡선 (b) VDD 변화에 대한 VREF 곡선 (c) power-up. Fig. 8. Simulatiob results of BGR: (a) VREF curve with respect to temperature, (b) VREF curve with respect to VDD, and (c) power-up.

JBJTBH_2018_v11n6_742_f0009.png 이미지

그림 9. BL sense amplifier 회로에 대한 power-on reset 모의실험 결과. Fig. 9. Simulation result of power-on reset for BL sense amplifier.

표 1. MTP 셀의 특성 비교. Table 1. Characteristic comparison of MTP cells.

JBJTBH_2018_v11n6_742_t0001.png 이미지

표 1. 64비트 FTP IP의 주요 특징. Table 2. Major specifications of 64-bit FTP IP.

JBJTBH_2018_v11n6_742_t0002.png 이미지

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