• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.204-209
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• 2016

The analyses on self-heating effect in 7 nm node non-rectangular Bulk FinFET device were performed using 3D device simulation with consideration to contact via and pad. From self-heating effect simulation, the position where the maximum lattice temperature occurs in Bulk FinFET device was investigated. Through the comparison of thermal resistance at each node, main heat transfer path in Bulk FinFET device can be determined. Self-heating effect with device parameter and operation temperature was also analyzed and compared. In addition, the impact of interconnects which are connected between the device on self-heating effect was investigated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.68-73
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• 2006

We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large $V_{TH}$ shifts over 2.5V at 12V/$10{\mu}s$ for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.988-991
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• 2011

We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different device structure as a bottom and top contact FET. Also, we used a $SiO_2$ as a gate insulator and analyzed using a current-voltage (I-V) characteristics of the bottom and top contact CuPc FET device. In order to discuss the channel formation, we were observed the capacitance-gate voltage(C-V) characteristics of the bottom and top contact CuPc FET device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.121-122
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• 2022

In this paper, the device performance with the structure of Nanosheet FET (NSFET) and FinFET is simulated through a three-dimensional device simulator. Current-voltage characteristics of NSFET and FinFET were simulated with respect to channel doping concentrations, and the performance such as threshold voltage and subthreshold swing extracted from the current-voltage characteristics was compared. NSFET flows more drain current and has a higher threshold voltage in current-voltage characteristics depending on channel doping concentration than that of FinFET. The subthreshold voltage swing (SS) of NSFET is steeper than that of FinFET

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.64-69
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• 2015

Self-heating effects of bulk and SOI FinFETs on device structure are examined with TCAD simulation. The degradation of drive current in SOI FinFET is severer than that of bulk one in steady-state condition as expected. However, it is shown that the dynamic self-heating effects of SOI FinFETs are comparable to those of bulk FinFETs for high speed logic operation, especially in realistic device structure.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.3
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• pp.283-289
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• 2014

This paper carries out a series of analysis of power system using Gallium Nitride (GaN) FET which has wide band gap (WBG) characteristics comparing to conventional Si MOSFET-used power system. At first, for comparison of each semiconductor device, the switching-transient parameter is quantitatively extracted from released information of GaN FET. And GaN FET model which reflect this dynamic property is configured. By using this model, the performance of GaN FET is analyzed comparing to Si MOSFET. Also, in order to enable a representative assessment on the power system level, Si MOSFET and GaN FET are applied to the most common structure of power system, full-bridge, and each power systems are compared based on various criteria, such as performance, efficiency and power density. The entire process is verified with the aid of mathematical analysis and simulation.

• Journal of Convergence for Information Technology
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• v.11 no.11
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• pp.159-165
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• 2021

A fin channel with a fin width of 20 nm and a gradually increased source/drain extension regions are fabricated on a bulk silicon wafer by using a three-dimensional selective oxidation. The detailed process steps to fabricate the proposed fin channel are explained. We are demonstrating their preliminary characteristics and properties compared with those of the conventional fin field effect transistor device (FinFET) and the bulk FinFET device via three-dimensional device simulation. Compared to control devices, the three-dimensional selective oxidation fin channel MOSFET shows a higher linear transconductance, larger drive current, and lower series resistance with nearly the same scaling-down characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.22-29
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• 2006

We demonstrate highly manufacturable Multi-channel Field Effect Transistor (McFET) on bulk Si wafer. McFET shows excellent transistor characteristics, such as $5{\sim}6 times higher drive current than planar MOSFET, ideal subthreshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency, maintaining the same source/drain resistance as that of a planar transistor due to the unique feature of McFET. And suitable threshold voltage ($V_T$) for SRAM operation and high static noise margin (SNM) are achieved by using TiN metal gate electrode.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.12-16
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• 2009

Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The sense FET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper, we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 450 V power MOSFET by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration $1.5{\times}10^{14}cm^{-3}$, size of $600{\um}m^2$ with $4.5\;{\Omega}$, and off-state leakage current below $50{\mu}A$. We offer the layout of the proposed sense FET to process actually. The offerd design and optimization methods are meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.30-37
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• 2006

In this article, we evaluated the structural merits and the validity of a partially insulated MOSFET (PiFET) through the fabrication of prototype transistors and an 80 nm 512M DDR DRAM with partially-insulated cell array transistors (PiCATs). The PiFETs showed the outstanding short channel effect immunity and off-current characteristics over the conventional MOSFET, resulting from self-induced halo region, self-limiting SID shallow junction, and reduced junction area due to PiOX layer formation. The DRAM with PiCATs also showed excellent data retention time. Thus, the PiFET can be a promising alternative for ultimate scaling of planar MOSFET.