JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Partially-insulated MOSFET (PiFET) and Its Application to DRAM Cell Transistor

  • Oh, Chang-Woo (Device Research Team, R&D Center, Samsung Electronics Co.) ;
  • Kim, Sung-Hwan (Device Research Team, R&D Center, Samsung Electronics Co.) ;
  • Yeo, Kyoung-Hwan (Device Research Team, R&D Center, Samsung Electronics Co.) ;
  • Kim, Sung-Min (Device Research Team, R&D Center, Samsung Electronics Co.) ;
  • Kim, Min-Sang (Device Research Team, R&D Center, Samsung Electronics Co.) ;
  • Choe, Jeong-Dong (Device Research Team, R&D Center, Samsung Electronics Co.) ;
  • Kim, Dong-Won (Device Research Team, R&D Center, Samsung Electronics Co.) ;
  • Park, Dong-Gun (Device Research Team, R&D Center, Samsung Electronics Co.)
  • Published : 2006.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this article, we evaluated the structural merits and the validity of a partially insulated MOSFET (PiFET) through the fabrication of prototype transistors and an 80 nm 512M DDR DRAM with partially-insulated cell array transistors (PiCATs). The PiFETs showed the outstanding short channel effect immunity and off-current characteristics over the conventional MOSFET, resulting from self-induced halo region, self-limiting SID shallow junction, and reduced junction area due to PiOX layer formation. The DRAM with PiCATs also showed excellent data retention time. Thus, the PiFET can be a promising alternative for ultimate scaling of planar MOSFET.

Keywords

References

  1. C. -W. Oh, S. -H. Kim, C. -S. Lee; J. -D. Choe, S. -A. Lee, S. -Y. Lee, K. -H. Yeo, H. -J. Jo, E. -J. Yoon, S. -J. Hyun, D. Park, and K. Kim, 'Highly manufacturable sub-50 nm high performance CMOSFET using real damascene gate process,' Technical Digest of VLSI, pp.147-148, June 2003
  2. W. -K. Yeh, W. -H. Wang, Y. -K. Fang, and F. -L. Yang., 'Temperature depedence of hot-carrierinduced degradation in 0.1 ${\mu}m$ SOI nMOSFETs with thin oxide,' IEEE Electron Device Leters., vol. 23, issue 7, no. 7, pp.425-427, July 2002 https://doi.org/10.1109/LED.2002.1015228
  3. D. Suh and J. Fossum, 'Dynamic floating-body instability in partially depleted SOI CMOS circuits,' Technical Digest of IEDM, pp.661-664, December 1994 https://doi.org/10.1109/IEDM.1994.383323
  4. O. Rozeau, J. Jomaah, J. Boussey, C. Raynaud, J. L. Pelloie, and F. Balestra, 'Impact of floating body and BS-tied architectures on SOI MOSFET's radio-frequency performances,' Technical Digest of SOI Conference, pp.124-125, October 2000 https://doi.org/10.1109/SOI.2000.892801
  5. A. Hiraiwa, M. Orasawara, N. Natsuaki, Y. Itoh, and H. Iwai, 'Local-field-enhancement model of DRAM retention failure,' Technical Digest of IEDM, pp.157-160, December 1998 https://doi.org/10.1109/IEDM.1998.746306
  6. S. Kamohara, K. Kubota, M. Moniwa, K. Ohyu, and A. Ogishima, 'Statistical PN junction leakage model with trap level fluctuation for Tref (refresh time)-oriented DRAM design,' Technical Digest of IEDM, pp.539-542, December1999 https://doi.org/10.1109/IEDM.1999.824211
  7. S. -M. Kim, C. ？W. Oh, J. ？D. Choe, C. ？S. Lee, and D. Park, 'A study on selective $Si_{0.8}Ge_{0.2}$ etch using polysilicon etchant diluted by $H_2O$ for threedimensional Si structure application,' SOI Tech. Dev. XI in international meeting of ECS, pp.81-85, April 2003