• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.204-209
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• 2016

The analyses on self-heating effect in 7 nm node non-rectangular Bulk FinFET device were performed using 3D device simulation with consideration to contact via and pad. From self-heating effect simulation, the position where the maximum lattice temperature occurs in Bulk FinFET device was investigated. Through the comparison of thermal resistance at each node, main heat transfer path in Bulk FinFET device can be determined. Self-heating effect with device parameter and operation temperature was also analyzed and compared. In addition, the impact of interconnects which are connected between the device on self-heating effect was investigated.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.68-73
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• 2006

We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large $V_{TH}$ shifts over 2.5V at 12V/$10{\mu}s$ for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.

• 한국전기전자재료학회논문지
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• 제24권12호
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• pp.988-991
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• 2011

We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different device structure as a bottom and top contact FET. Also, we used a $SiO_2$ as a gate insulator and analyzed using a current-voltage (I-V) characteristics of the bottom and top contact CuPc FET device. In order to discuss the channel formation, we were observed the capacitance-gate voltage(C-V) characteristics of the bottom and top contact CuPc FET device.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2022년도 추계학술대회
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• pp.121-122
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• 2022

본 논문은 Nanosheet FET(NSFET)와 FinFET의 구조를 갖는 소자 성능을 조사하기 위해서 3차원 소자 시뮬레이터를 이용하여 시뮬레이션한 결과를 소개한다. NSFET와 FinFET의 채널 도핑 농도에 따른 전류-전압 특성을 시뮬레이션하였고, 그 전류-전압 특성으로부터 추출한 문턱전압, 문턱전압이하 기울기 등의 성능을 비교하였다. NSFET이 FinFET보다 채널 도핑 농도에 따른 전류-전압 특성에서 드레인 전류가 더 많이 흐르며 더 높은 문턱전압을 갖는다. 문턱전압이하 기울기는 NSFET가 FinFET보다 더 가파른 기울기를 갖는다.

• 전자공학회논문지
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• 제52권10호
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• pp.64-69
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• 2015

본 연구에서는 실제적 구조를 가지는 bulk와 SOI FinFET에서의 self-heating 효과를 3차원 TCAD 전산모사를 통하여 분석하였다. 기존 연구들에서와 마찬가지로 self-heating 효과에 의해 나타나는 정적인 구동전류의 감소는 SOI FinFET에서 bulk FinFET보다 더 심각함을 보여주고 있다.. 그러나 고속의 logic 동작 및 실제적 구조를 감안하면 SOI FinFET에서의 동적 self-heating 효과는 bulk FinFET과 큰 차이가 없음을 강조한다.

• 전력전자학회논문지
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• 제19권3호
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• pp.283-289
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• 2014

This paper carries out a series of analysis of power system using Gallium Nitride (GaN) FET which has wide band gap (WBG) characteristics comparing to conventional Si MOSFET-used power system. At first, for comparison of each semiconductor device, the switching-transient parameter is quantitatively extracted from released information of GaN FET. And GaN FET model which reflect this dynamic property is configured. By using this model, the performance of GaN FET is analyzed comparing to Si MOSFET. Also, in order to enable a representative assessment on the power system level, Si MOSFET and GaN FET are applied to the most common structure of power system, full-bridge, and each power systems are compared based on various criteria, such as performance, efficiency and power density. The entire process is verified with the aid of mathematical analysis and simulation.

• 융합정보논문지
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• 제11권11호
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• pp.159-165
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• 2021

본 삼차원 선택적 산화를 이용하여 20 nm 수준의 핀 폭과 점진적으로 증가된 소스/드레인 확장 영역을 갖는 핀 채널을 벌크 실리콘 기판에 제작하였다. 제안된 기법을 이용하여 삼차원 소자를 제작하기 위한 공정기법 및 단계를 상세히 설명하였다. 삼차원 소자 시뮬레이션을 통해, 제안된 소자의 주요 특징과 특성을 기존 FinFET 및 벌크 FinFET 소자와 비교하였다. 제안된 삼차원 선택적 산화 방식의 핀 채널 MOSFET는 기존의 소자들과 비교하여 더 큰 구동 전류, 더 높은 선형 트랜스컨덕턴스, 더 낮은 직렬 저항을 가지며, 거의 유사한 수준의 소형화 특성을 보이는 것을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.22-29
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• 2006

We demonstrate highly manufacturable Multi-channel Field Effect Transistor (McFET) on bulk Si wafer. McFET shows excellent transistor characteristics, such as $5{\sim}6 times higher drive current than planar MOSFET, ideal subthreshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency, maintaining the same source/drain resistance as that of a planar transistor due to the unique feature of McFET. And suitable threshold voltage ($V_T$) for SRAM operation and high static noise margin (SNM) are achieved by using TiN metal gate electrode.

• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.12-16
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• 2009

Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The sense FET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper, we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 450 V power MOSFET by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration $1.5{\times}10^{14}cm^{-3}$, size of $600{\um}m^2$ with $4.5\;{\Omega}$, and off-state leakage current below $50{\mu}A$. We offer the layout of the proposed sense FET to process actually. The offerd design and optimization methods are meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.30-37
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• 2006

In this article, we evaluated the structural merits and the validity of a partially insulated MOSFET (PiFET) through the fabrication of prototype transistors and an 80 nm 512M DDR DRAM with partially-insulated cell array transistors (PiCATs). The PiFETs showed the outstanding short channel effect immunity and off-current characteristics over the conventional MOSFET, resulting from self-induced halo region, self-limiting SID shallow junction, and reduced junction area due to PiOX layer formation. The DRAM with PiCATs also showed excellent data retention time. Thus, the PiFET can be a promising alternative for ultimate scaling of planar MOSFET.