• Journal of the Semiconductor & Display Technology
• /
• v.22 no.2
• /
• pp.104-111
• /
• 2023

The semiconductor industry, which relies on global supply chains, has recently been facing longer lead time for material procurement due to supply chain uncertainties. Moreover, since increasing customer satisfaction and reducing inventory costs are in a trade-off relationship, it is challenging to determine the appropriate safety stock level under demand and lead time uncertainties. In this paper, we propose a framework for determining safety stock levels by utilizing the optimization method to determine the optimal safety stock level. Additionally, we employ a linear regression method to analyze customer satisfaction scores and inventory costs based on variations in lead time and demand. To verify the effectiveness of the proposed framework, we compared safety stock levels obtained by the regression equations with those of the conventional method. The numerical experiments demonstrated that the proposed method successfully reduces inventory costs while maintaining the same level of customer satisfaction when lead time increases.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.1047-1050
• /
• 2009

The two approaches to improve the stability of oxide TFTs are described. First approach is the optimization of device architecture including MIS structure and passivation layer using conventional InGaZnO semiconductor channel layer. Second approach is to develop the new kinds of oxide semiconductor materials, which is very robust and stable against the gate bias stress and thermal stress.

• Proceedings of the KIPE Conference
• /
• 2015.07a
• /
• pp.159-160
• /
• 2015

Recently, it is increased to use the portable device with small size. It is also increasing for demand of a small size adapter. To reduce the size of components, switching frequency has to be increased. But it causes higher switching loss and temperature of components. Especially, the temperature of adapter must be limited because adapter can be easily touched when portable device is being charged. To reduce temperature of adapter, high efficiency is essential. To solve this problem, this paper proposes design of resonance frequency optimization for LLC converter with high efficiency and low temperature of passive components.

• Industrial Engineering and Management Systems
• /
• v.4 no.1
• /
• pp.54-67
• /
• 2005

This paper provides an evaluation of an optimization-based, multiple-input double-output (MIDO) run-to-run (R2R) control scheme for general semiconductor manufacturing processes. The controller in this research, termed adaptive dual response optimizing controller (ADROC), can serve as a process optimizer as well as a recipe regulator between consecutive runs of wafer fabrication. In evaluation, it is assumed that the equipment model could be appropriately described by a pair of second-order polynomial functions in terms of a set of controllable variables. Of practical relevance is to consider a drifting effect in the equipment model since in common semiconductor practice the process tends to drift due to machine aging and tool wearing. We select a typical application of R2R control to chemical mechanical planarization (CMP) in semiconductor manufacturing in this evaluation, and there are five different CMP process scenarios demonstrated, including mean shift, variance increase, and IMA disturbances. For the controller, ADROC, an on-line estimation technique is implemented in a self-tuning (ST) control manner for the adaptation purpose. Subsequently, an ad hoc global optimization algorithm based on the dual response approach, arising from the response surface methodology (RSM) literature, is used to seek the optimum recipe within the acceptability region for the execution of next run. The main components of ADROC are described and its control performance is assessed. It reveals from the evaluation that ADROC can provide excellent control actions for the MIDO R2R situations even though the process exhibits complicated, nonlinear interaction effects between control variables, and the drifting disturbances.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.1
• /
• pp.134-138
• /
• 2023

This study focuses on the analysis of the results of computational fluid dynamics simulations of mist-chemical vapor deposition for the growth of an epitaxial wafer in power semiconductor technology using artificial intelligence techniques. The conventional approach of predicting the uniformity of the deposited layer using computational fluid dynamics and design of experimental takes considerable time. To overcome this, artificial intelligence method, which is widely used for optimization, automation, and prediction in various fields, was utilized to analyze the computational fluid dynamics simulation results. The computational fluid dynamics simulation results were analyzed using a supervised deep neural network model for regression analysis. The predicted results were evaluated quantitatively using Euclidean distance calculations. And the Bayesian optimization was used to derive the optimal condition, which results obtained through deep neural network training showed a discrepancy of approximately 4% when compared to the results obtained through computational fluid dynamics analysis. resulted in an increase of 146.2% compared to the previous computational fluid dynamics simulation results. These results are expected to have practical applications in various fields.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.2
• /
• pp.192-198
• /
• 2017

In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage ($V_{amb}$) and double gate structure is applied to improve on-current ($I_{ON}$) and subthreshold swing (SS). We discussed the fin width ($W_S$), body doping concentration, sidewall width ($W_{side}$), drain and gate underlap distance ($X_d$), source doping distance ($X_S$) and pocket doping length ($X_P$) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high $I_{ON}$ of $1.2{\times}10^{-3}A/{\mu}m$ and low $V_{amb}$ of -2.0 V.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.240-249
• /
• 2004

In the present paper efforts have been made to optimize InAlAs/InGaAs HEMT by enhancing the effective gate voltage ($(V_c-V_off)$) using pulsed doped structure from uniformly doped to delta doped for microwave frequency applications and reliability. The detailed design criteria to select the proper design parameters have also been discussed in detail to exclude parallel conduction without affecting the del ice performance. Then the optimized value of $V_c-V_off$and breakdown voltages corresponding to maximum value of transconductance has been obtained. These values are then used to predict the transconductance and cut-off frequency of the del ice for different channel depths and gate lengths.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.40-41
• /
• 2005

In this study, we proposed CMP micro-scratches generated by contaminative particle which existed on the wafer surface prior to CMP process. The CMP micro-scratches are one of the slurry abrasive related damage. To reduce the micro-scratches, research efforts have been devoted to the optimization of slurry abrasive size distribution. In addition of slurry abrasive, it was found that contaminative particles also were major CMP micro-scratch source.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.3
• /
• pp.165-169
• /
• 2012

Power semiconductor devices are widely used as high voltage applications to inverters and motor drivers, etc. The blocking voltage is one of the most important parameters for power semiconductor devices. And cause of junction curvature effects, the breakdown voltage of the device edge and device unit cells was found to be lower than the 'ideal' breakdown voltage limited by the semi-infinite junction profile. In this paper, Propose the methods for field ring design by DOE (Design of Experimentation). So The field ring can be improve for breakdown voltage and optimization.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.150-151
• /
• 2006

$Si_{0.88}Ge_{0.12}$/Si heterostructure channels grown by RPCVD were employed to n-type metal oxide semiconductor field effect transistors(MOSFETs), and their electrical properties were investigated. SiGe nMOSFETs presented very high transconductance compared to conventional Si-bulk MOSFETs, regardless substantial drawbacks remaining in subthreshold-slope, $I_{off}$, and leakage current level. It looks worthwhile to utilize excellent transconductance properties into rf applications requesting high speed and amplification capability, although optimization works on both device structure and unit processes are necessary for enhanced isolation and reduced power dissipation.