JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Optimization of Double Gate Vertical Channel Tunneling Field Effect Transistor (DVTFET) with Dielectric Sidewall

  • WANG, XIANGYU (Department ofElectronic Engineering, Myongji University) ;
  • Cho, Wonhee (Department ofElectronic Engineering, Myongji University) ;
  • Baac, Hyoung Won (School of Electronic and Electrical Engineering, Sungkyunkwan University) ;
  • Seo, Dongsun (Department ofElectronic Engineering, Myongji University) ;
  • Cho, Il Hwan (Department ofElectronic Engineering, Myongji University)
  • Received : 2016.08.13
  • Accepted : 2016.09.28
  • Published : 2017.04.30
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Abstract

In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage ($V_{amb}$) and double gate structure is applied to improve on-current ($I_{ON}$) and subthreshold swing (SS). We discussed the fin width ($W_S$), body doping concentration, sidewall width ($W_{side}$), drain and gate underlap distance ($X_d$), source doping distance ($X_S$) and pocket doping length ($X_P$) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high $I_{ON}$ of $1.2{\times}10^{-3}A/{\mu}m$ and low $V_{amb}$ of -2.0 V.

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References

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