• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7B
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• pp.1081-1090
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• 2010

$0.18{\mu}m$ CMOS UHF RFID tag frontend is presented in this paper. Several key components are highlighted: the voltage multiplier based on the threshold voltage terminated circuit, the demodulator using current mode, and the clock generator. For standard compliance, all designed components are under the EPC Global Class-1 Generation-2 UHF RFID protocol. Backscatter modulation uses the pulse width modulation scheme. Overall performance of the proposed tag chip was verified with the evaluation board. Prototype Tag Chip dimension is neary 0.77mm2 ; According to the simulation results, the reader can successfully interrogate the tag within 1.5m. where the tag consumes the power about $71{\mu}W$.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.107-115
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• 2014

The reduced-bit transform based bit-plane matching algorithm (BPM) can obtain the block matching result through its simple calculation and hardware design compared to the conventional block matching algorithms (BMAs), but the block matching accuracy of BPMs is somewhat low. In this paper, reduced-bit transform based sum of the absolute difference (R-SAD) is proposed to improve the block matching accuracy in comparison with the conventional BPMs and it is shown that the matching process can be obtained using the logical operations. Firstly, this method transforms the current and the reference images into their respective 2-bit images and then a truth table is obtained from the relation between input and output 2-bit images. Next, a truth table is simplified by Karnaugh map and the absolute difference is calculated by using simple logical operations. Finally, the simulation results show that the proposed R-SAD can obtain higher accuracy in block matching results compared to the conventional BPMs through the PSNR analysis in the motion compensation experiments.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.172-180
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• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.

• Journal of Satellite, Information and Communications
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• v.9 no.3
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• pp.86-90
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• 2014

A DC-DC Converter operates in CCM(Continuous Coundcution Mode), DCM(Discontinuous Conduction Mode), CRM(Critical Conduction Mode). The CRM is boundary between CCM and DCM. If a DC-DC converter is designed to operate in CRM, its inductor volume can decrease and power loss which caused by switch and diode can decrease. In this paper, the DC-DC converter which operates in CRM is applied to a solar array regulator(SAR) for the satellite. The switching frequency of the CRM boost SAR changes according to input and output condition. The switching frequency limit logic is applied to limit the maximum switching frequency. Meanwhile, the small signal transfer function of the CRM boost SAR is simple, so the controller design is also simple. In this paper, the small signal transfer function from control reference to solar array voltage is induced. And the voltage controller is designed based on the small signal transfer function. Finally, the CRM boost SAR is verified by simulation.

• Journal of Electrical Engineering and Technology
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• v.12 no.1
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• pp.78-90
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• 2017

This paper presents the design of closed loop controllers operating a single-phase AC-DC three-level converter for improving power quality at AC mains. Closed loop inhibits outer voltage controller and inner current controller. Simulations of three level converter with three different voltage and current controller combinations such as PI-Hysteresis, Fuzzy-Hysteresis and Fuzzy tuned PI-Hysteresis are carried out in MATLAB/Simulink. Performance parameters such as input power factor and source current total harmonic distortion (THD) are considered for comparison of the three controller combinations. The fuzzy-tuned PI voltage controller with hysteresis current controller combination provides a better result, with a source-current THD of 0.93% and unity power factor without any source side filter for the three level converter. For load variations of 25% to 100%, a THD of less than 5% is obtained with a maximum value of only 1.67%. Finally, the fuzzy-tuned PI voltage with hysteresis controller combination is implemented in a Xilinx Spartan-6 XC6SLX25 FPGA board for experimental validation of power quality enhancement. A prototype 100 W, 0-24-48 V as output converter is considered for the testing of controller performance. A source-current THD of 1.351% is obtained in the experimental study with a power factor near unity. For load variations of 25% to 100%, the THD is found to be less than 5%, with a maximum value of only 2.698% in the experimental setup which matches with the simulation results.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.10
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• pp.67-76
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• 2004

This paper improves existing 'fly-the-wire' based autonomous station-keeping system, suitable for geostationary satellite and introduces results of computer simulations conducted to verify the algorithm. The on-board stationkeeping system receives pseudo-range signals from two ground equipments located with long baseline, determines the orbit error in realtime and generates orbit control commands. To reduce fuel consumption, this paper proposes an on-board orbit control logic using modified fly-the-wire method. The modified fly-the-wire method de-couples error components into two dynamic modes, harmonic and linear motion. The harmonic error components are removed by applying output commands produced by feedback controller, and the linear motions are controlled by the correction ${\Delta}V\;s$ added to reference maneuvers. The reference maneuvers are generated through the ground based computer simulation and embedded or uploaded into the on-board computer with time tags. Finally, the performance of the proposed algorithm is verified through a series of computer simulations.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.1
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• pp.16-21
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• 2002

In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.4
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• pp.173-179
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• 2002

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.10-16
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• 1999

This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.1
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• pp.101-110
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• 2004

The robots that will be needed in the near future are human-friendly robots that are able to coexist with humans and support humans effectively. To realize this, humans and robots need to be in close proximity to each other as much as possible. Moreover, it is necessary for their interactions to occur naturally. It is desirable for a robot to carry out human following, as one of the human-affinitive movements. The human-following robot requires several techniques: the recognition of the moving objects, the feature extraction and visual tracking, and the trajectory generation for following a human stably. In this research, a predictable intelligent space is used in order to achieve these goals. An intelligent space is a 3-D environment in which many sensors and intelligent devices are distributed. Mobile robots exist in this space as physical agents providing humans with services. A mobile robot is controlled to follow a walking human using distributed intelligent sensors as stably and precisely as possible. The moving objects is assumed to be a point-object and projected onto an image plane to form a geometrical constraint equation that provides position data of the object based on the kinematics of the intelligent space. Uncertainties in the position estimation caused by the point-object assumption are compensated using the Kalman filter. To generate the shortest time trajectory to follow the walking human, the linear and angular velocities are estimated and utilized. The computer simulation and experimental results of estimating and following of the walking human with the mobile robot are presented.