Journal of the Institute of Electronics Engineers of Korea TE (대한전자공학회논문지TE)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

(A Dual Type PFD for High Speed PLL)

고속 PLL을 위한 이중구조 PFD

  • 조정환 (김포대학 디지털시스템전공) ;
  • 정정화 (한양대학교 전자전기 컴퓨터공학부)
  • Published : 2002.03.01
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.

본 논문에서는 TSPC(True Single Phase Clocking) CMOS 회로를 이용하여 출력특성을 향상시킨 고속 PLL을 위한 이중구조 PFD(Phase Frequency Detector)를 제안한다. 넓은 dead zone과 긴 지연시간을 갖고 있는 기존의 3-state PFD는 고속 동작에 사용되는 PLL(Phase-Locked Loop)에서 사용하는 것은 부적합하다. 이러한 3-state PFD의 단점을 해결하기 위하여 다이내믹 CMOS 논리회로로 구현된 다이내믹 PFD는 duty cycle의 변화에 따라 지터 잡음을 발생하는 문제점을 갖는다. 이러한 문제를 해결하기 위하여 TSPC 회로와 이중구조를 갖도록 설계되어 제안된 PFD는 dead zone과 duty cycle의 제한조건을 개선하였고, 지터잡음과 응답특성을 개선하였다. 즉, 이중구조를 갖는 PFD는 상승에지에서 동작하는 P-PFD(Positive edge triggered PFD)와 하강에지에서 동작하는 N-PFD(Negative edge triggered PFD)로 구성하여 이득을 증가시켜 응답특성을 개선한다. 제한된 내용의 입증을 위하여 Hspice 시뮬레이션을 수행하였다. 제안된 PFD는 dead zone이 존재하지 않으며, duty cycle의 변화에도 안정된 결과를 나타내며 응답특성이 우수함을 확인할 수 있었다.

Keywords

References

  1. R. E. Best, Phase-Locked Loops Theory, Design, and Applications, 3rd ed., New York : McGraw-Hill, 1997
  2. William F. Egan, Frequency Synthesis by Phase Lock, 2nd ed., John Willey & Sons, Inc., 2000
  3. Harufusa Kondoh et al., 'A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector,' IEICE Trans Electron., Vol. E78 C. No. 4, pp. 381-388, April 1995
  4. Sang-O Jeon, et al., 'Phase/frequency Detectors for High-Speed PLL Applications,' Electronics Letters, Vol. 34, No. 22, pp. 2120-2121, Oct. 1998 https://doi.org/10.1049/el:19981493
  5. Henrik O. Johansson, 'A Simple Precharged CMOS Phase Frequency Detector,' IEEE JSSC, Vol. 33, No. 2, pp. 295-299, Feb. 1998
  6. Jung-Dong Cho, et al., 'A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops,' IEICE Trans Fundamentals, Vol. E82-A, No. 11, pp. 2514-2520, Nov. 1999
  7. Y. Sumi, et al., 'Dead-zoneless PLL Frequency Synthesizer by Hybrid Phase Detectors,' in Proc. IEEE JSSC, Vol. 4, pp. 410-414, July 1999
  8. Tae-Hun Kim and Beomsup Kim, 'Dual-loop Digital for Adaptive Clock Recovery,' in Proc. IEEE JSSC, Vol. 4, pp. 410-414, July 1999
  9. J. Yuan and C. Svensson, 'New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings,' IEEE JSSC, Vol.32, No. 1, pp. 62-69, Jan. 1997