Journal of the Institute of Electronics Engineers of Korea TC (대한전자공학회논문지TC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of a High-speed Decision Feedback Equalizer using the Constant-Modulus Algorithm

CMA 알고리즘을 이용한 고속 DFE 등화기 설계

  • Published : 2002.04.01
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Abstract

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.

본 논문은 DFE (Decision Feedback Equalizer)구조와 CMA (Constant Modulus Algorithm), 그리고 LMS (Least Mean Square) 알고리즘을 이용한 등화기에 대하여 기술한다. DFE 구조는 기존의 transversal 구조의 등화기에 비하여 빠른 채널 적응 속도와 낮은 BER (Bit Error Rate) 값을 가지며 ISI(Intersymbol Interference)가 심한 환경에서도 좋은 성능을 나타낸다. 본 등화기는 16/64 QAM(Quadrature Amplitude Modulation) 변복조 방식에 적용할 수 있으며, 고속으로 동작할 수 있도록 고속의 곱셈기와 많은 수의 CSA (Carry Save Adder)를 사용하였다. COSSAP/sup TM/ 캐드 툴을 사용하여 부동 소수점 모델과 고정 소수점 모델을 개발하였으며, VHDL 모델을 개발하였다. 시뮬레이션 결과에 따라 feedback 부분과 feedforward 부분에 각각 12개와 8개의 탭을 사용하였으며, 다중 경로 페이딩 채널에서 BER이 10-6일 때를 기준으로 보면 등화기를 사용하지 않은 채널의 BER 보다 SNR(Signal to Noise Ratio)이 4dB 정도 향상되었다. SYNOPSYS/sup TM/ 캐드 툴과 삼성의 0.5 ㎛ standard cell library (STD80) 를 이용하여 로직 합성을 수행하였으며, 전체 게이트 카운트는 약 13만개를 보였다.

Keywords

References

  1. Haykin, ADAPTIVE FILTER THEORY-third edition, Prentice-Hall, 1996
  2. Ramjee Prasad, Universal Wireless Personal Communications, Boston-London, Artech House Publishers, 1998
  3. Gordon L. Stuber, Principles of MOBILE COMMUNICATION- second edition, Kluwer Academic Publishers, 2001
  4. Theodore S. Rappaport, Wireless Communications : Principles and Practice, Prentice-Hall, 1996
  5. Ki H. Park, Dae K. Shin, Jun S. Lee and Myung H. Sunwoo, 'Design of a QPSK/16 QAM LMDS Downstream Receiver ASIC Chip', in Proc. IEEE Workshop on SIGNAL PROCESSING SYSTEMS Design and Implementation, Oct. 2000, pp.210-217 https://doi.org/10.1109/SIPS.2000.886718
  6. Jae Chon Lee, Chong Kwan Un, 'Performance of Transform Domain LMS Adaptive Digital Filters', IEEE Transactions on Acoustics, Speech and Signal Processing, Vol.ASSP-34, No.3, pp.499-510, June, 1986 https://doi.org/10.1109/TASSP.1986.1164850
  7. J. Yang, J. J. Werner and Jr., G. A. Dumont, 'The Multimodulus Blind Equalization Algorithm', in Proc. Thirteenth Int'l Conf. On Digital Signal Processing, Santorini, Greece, July 2-4, 1997
  8. Zhi Ding, Ye (Geoffrey) Li, Blind Equalization and Identification, Marcel Dekker, 2001
  9. C. R. Johnson, Jr. et al., 'Blind equalization using the constant modulus criterion: A review', Proc. IEEE(Special Issue on Blind System Identification and Estimation), Vol.86, pp.1927-1950, Oct. 1998 https://doi.org/10.1109/5.720246
  10. SeokHee Hong, DaeKyo Shin, MyungHoon Sunwoo, 'A DFE Structure Equalizer ASIC Chip Using Constant Modulus Algorithm', IDEC Conference 2000, 천안, 2000년 8월 ,pp.49-52
  11. Fco. Rodrigo, P. Cavalcanti, Joao Cesar M. Mota, 'A Predictive Constant Modulus Algorithm for Blind Equalization in QAM Systems', IEEE International Conference on Communications, Vol.2/3, pp.1080-1084, 1997 https://doi.org/10.1109/ICC.1997.610051
  12. John R. Treichler, Brian G. Agee, 'A New Approach to Multipath Correction of Constant Modulus Signals', IEEE Transactions on Acoustic, Speech and Signal Processing, Vol. ASSP-31, No. 2, pp.459-472, April, 1983 https://doi.org/10.1109/TASSP.1983.1164062
  13. Kihyuk Park, Daekyo Shin, Junsung Lee and Myung H. Sunwoo, 'A QPSK/16 QAM Receiver Chip for LMDS Application', in Proc. the Second IEEE Asia Pacific Conference on ASICs, Cheju, Korea, pp.207-210, Aug. 2000 https://doi.org/10.1109/APASIC.2000.896945
  14. Daekyo Shin, Ki Hyuk Park and Myung H. Sunwoo, 'A 64/256 QAM Receiver Chip for High-speed Communications', in Proc. IEEE International ASIC/SOC Conference, Washington DC. U.S.A., pp. 214-218, Sep. 2000 https://doi.org/10.1109/ASIC.2000.880704
  15. SeungJoon Hwang, DaeKyo Shin and MyungHoon Sunwoo, 'A QPSK/16 QAM ASIC Chip for LMDS Application', IDEC Conference 2000, 천안, pp.81-84, 2000년8월
  16. 신대교, 홍석희, 선우명훈, 'Blind 알고리즘을 이용한 DFE Equalizer의 설계', 1999년도 제12회 신호처리합동학술대회, 포항공과대학, pp.1031-1034, 1999년 10월
  17. George Mathew, B. Farhang-Beroujeny, Roger W. Wood, 'Design of Multilevel Decision Feedback Equalizers', IEEE Transactions on Magnetics, Vol.33, No.6, pp.4528-4542, November 1997 https://doi.org/10.1109/20.649891
  18. Hyeongseok Yu, Byung Wook Kim, Yeon gon Cho, Jun Dong Cho, Jea Woo Kim, Jae Kon Lee, Hyeon Cheol Park, Ki Won Lee, 'Area Efficient and Reusalble VLSL Architecture of Dedision Feedback Equalizer for QAM Modern', proc., ASP-DAC2001, pp.404-407, January, 2001