• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.6
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• pp.266-271
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• 2001

In this paper, a controller design for coreless linear synchronous motor is proposed. The designed controller is mainly composed of speed and current control, which are carried out by the high-speed digital signal processor(DSP). In addition the PWM inverter is controlled by space voltage PWM method. This system is implemented using by 32-bit DSP(TMS320C31), a high-integrated logic device(EPM940), and IPM(Intelligent Power Modules) for compact and powerful system design. The experimental results show the effective performance of controller for coreless linear synchronous motor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.11
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• pp.994-999
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• 2006

For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1991.10a
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• pp.86-91
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• 1991

A capability of performing the optical logic and arithmetic operations is followed by an effective encoding technique. In this paper, we proposed the color light encoding technique. By using this encoding technique, the space bandwidth product(SBP) is minimized in the output plane. In addition, we proposed the pre-operation pro-carry processing method that performs faster than the same time operation and carry processing method in optical computing. We proposed that the color liquid crystal device(CLCD) is used as the encoded color light input source.

• Proceedings of the KAIS Fall Conference
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• 2003.06a
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• pp.208-210
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• 2003

In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor fer a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.1-8
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• 2003

In this study, the high performance BCD device structure which satisfies the high voltage and fast switching speed characteristics is devised. Through the process and device simulation, optimal process spec. & device spec. are designed. We adapt double buried layer structure, trench isolation process, n-/p-drift region formation and shallow junction technology to optimize an electrical property as mentioned above. This I.C consists of 20V level high voltage bipolar npn/pnp device, 60V level LDMOS device, a few Ampere level VDMOS, 20V level CMOS device and 5V level logic CMOS.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.64-69
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• 2015

Self-heating effects of bulk and SOI FinFETs on device structure are examined with TCAD simulation. The degradation of drive current in SOI FinFET is severer than that of bulk one in steady-state condition as expected. However, it is shown that the dynamic self-heating effects of SOI FinFETs are comparable to those of bulk FinFETs for high speed logic operation, especially in realistic device structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.302-317
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• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• Korea Information Processing Society Review
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• v.11 no.6
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• pp.56-75
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• 2004

In this article we address some system characteristics and challenging issues in developing Context-aware Middleware for Ubiquitous Computing. The functionalities of a Context-aware Middleware includes gathering context data from hardware/software sensors, reasoning and inferring high-level context data, and disseminating/delivering appropriate context data to interested applications/services. The Middleware should facilitate the query, aggregation, and discovery for the contexts, as well as facilities to specify their privacy policy. Following a formal context model using ontology would enable syntactic and semantic interoperability, and knowledge sharing between different domains. Moddleware should also provide different kinds of context classification mechanical as pluggable modules, including rules written in different types of logic (first order logic, description logic, temporal/spatial logic, fuzzy logic, etc.) as well as machine-learning mechanical (supervised and unsupervised classifiers). Different mechanisms have different power, expressiveness and decidability properties, and system developers can choose the appropriate mechanism that best meets the reasoning requirements of each context. And finally, to promote the context-trigger actions in application level, it is important to provide a uniform and platform-independent interface for applications to express their need for different context data without knowing how that data is acquired. The action could involve adapting to the new environment, notifying the user, communicating with another device to exchange information, or performing any other task.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.1-7
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• 2008

Magnetic Tunneling Junction (MTJ) has been used as a nonvolatile universal storage element mainly in memory technology. However, according to several recent studies, magneto-logic using MTJ elements show much potential in substitution for the transistor-based logic device. Magneto-logic based on MTJ can maintain the data during the power-off mode, since an MTJ element can store the result data in itself. Moreover, just by changing input signals, the full logic functions can be realized. Because of its programmability, it can embody the reconfigurable magneto-logic circuit in the rigid physical architecture. In this paper, we propose a novel 3-bit arbitrary magneto-logic circuit beyond the simple combinational logic or the short sequential one. We design the 3-bit magneto-logic which has the most complexity using MTJ elements and verify its functionality. The simulation results are presented with the HSPICE macro-model of MTJ that we have developed in our previous work. This novel magneto-logic based on MTJ can realize the most complex logic function. What is more, 3-bit arbitrary logic operations can be implemented by changing gate signals of the current drivel circuit.