• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.3-6
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• 2004

Power semiconductor devices are being compact, high performance and intelligent thanks to recent remarkable developments of silicon design, process and related packaging technologies. Developments of MOS-gate transistors such as MOSFET and IGBT are dominant thanks to their advantages on high speed operation. In conjunction with package technology, silicon technologies such as trench, charge balance and NPT will support future power semiconductors. In addition, wide band gap material such as SiC and GaN are being studies for next generation power semiconductor devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.7
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• pp.500-505
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• 2012

In this study, the influence of the intermolecular distance on the charge mobility in a pentacene thin-film was investigated. In order to increase the mobility which depends on the ${\pi}$-overlap between molecules, the intermolecular distance was shortened by compressive force along the conduction channel. Pentacene thin-film was fabricated on flexible substrates bent outward at different radii to stretch the gate dielectric surface and then the substrates were unbent, producing the compressive force to the film. The result showed that the mobility increased proportionally to the strain applied during the pentacene deposition and the molecular packing inside a grain was not optimal for the charge transport.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.136-136
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• 2011

반도체 및 전자기기 산업에 있어서 NVM은 아주 중요한 부분을 차지하고 있다. NVM은 디스플레이 분야에 많은 기여를 하고 있는데, 측히 AMOLED에 적용이 가능하여 온도에 따라 변하는 구동 전류, 휘도, color balance에 따른 문제를 해결하는데 큰 역할을 한다. 본 연구에서는 bottom gate 구조의 nc-Si NVM 실험을 진행하였다. P-type silicon substrate (0.01~0.02 ${\Omega}-cm$) 위에 Blocking layer 층인 SiO2 (SiH4:N2O=6:30)를 12.5nm증착하였고, Charge trap layer 층인 SiNx (SiH4:NH3=6:4)를 20 nm 증착하였다. 마지막으로 Tunneling layer 층인 SiOxNy은 N2O (2.5 sccm) 플라즈마 처리를 통해 2.5 nm 증착하였다. 이러한 ONO 구조층 위에 nc-Si을 50 nm 증착후에 Source와 Drain 층을 Al 120 nm로 evaporator 이용하여 증착하였다. 제작한 샘플을 전기적 특성인 Threshold voltage, Subthreshold swing, Field effect mobility, ON/OFF current ratio, Programming & Erasing 특성, Charge retention 특성 등을 알아보았다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.67.2-67.2
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• 2012

Graphene is expected to have a significant impact in various fields in the foreseeable future. For example, graphene is considered to be a promising candidate to replace indium tin oxide (ITO) as transparent conductive electrodes in optoelectronics applications. We report the tunability of the wavelength of localized surface plasmon resonance by varying the distance between graphene and Au nanoparticles [1]. It is estimated that every nanometer of change in the distance between graphene and the nanoparticles corresponds to a resonance wavelength shift of ~12 nm. The nanoparticle-graphene separation changes the coupling strength of the electromagnetic field of the excited plasmons in the nanoparticles and the antiparallel image dipoles in graphene. We also show a hysteresis in the conductance and capacitance can serve as a platform for graphene memory devices. We report the hysteresis in capacitance-voltage measurements on top gated bilayer graphene which provide a direct experimental evidence of the existence of charge traps as the cause for the hysteresis [2]. By applying a back gate bias to tune the Fermi level, an opposite sequence of switching with the different charge carriers, holes and electrons, is found [3]. The charging and discharging effect is proposed to explain this ambipolar bistable hysteretic switching.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.11 no.3
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• pp.313-320
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• 1999

A PFC(Perfluorocarbon) heat pipe has been used recently for cooling of GTO(gate turn off) thyristors or diodes in electric commuter trains. The present study was conducted to determine heat transport limitation of a PFC heat pipe which is one of the important parameters in heat pipes design. The variables such as tube diameter, fill charge ratio, internal surface structure and operating temperature were examined by way of experiment. Experimental data showed that the heat transport limitation of PFC heat pipe was considerably low and mostly dependent on tube diameter, with the value of 440~500W for d$o$/=22.23mm and 150~200W for d$o$=15.88mm. The other parameters had negligible effects, except for the case of small charge ratio less than 30%. Some correlations proposed by previous studies were in agreement with data from this study within 10~30%.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.7
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• pp.1121-1127
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• 1994

The accelerated degradation phenomena in amorphous silicon thin film transistors due to both electrical stress and visible light illumination under the elevated temperature have been investigated systematically as a function of gate bias, light intensity, and stress time. It has been found that, in case of electrical stress, the thrshold voltage shifts of a-Si:H TFT's may be attributed to the defect creation process at the early stage, while the charge trapping phenomena may be dominant when the stressing periods exceed about 2 hours. It has been also observed that the degradation in the device characteristics of a-Si:H TFT's is accelerated due to multiple stress effects, where the defect creation mechanism may be more responsible for the degradation rather than the charge trapping mechanism.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.71-74
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• 1998

In this Paper, we investigate the electrical properties of ultra-thin(70${\AA}$) nitrided(NO) and reoxidized nitrided oxide(ONO) film that ale considered to be premising candidates for replacing conventional silicon dioxide film in ULSI level integration. we studied I$\sub$g/-V$\sub$g/ characteristics to know the effect of nitridation and reoxidation on the current conduction, leakage current time-dependent dielectric breakdown(TDDB) to evaluate charge-to-breakdown(Q$\sub$bd/), and the effect of stress temperature(25, 50, 75, 100$^{\circ}C$) and compared to those with thermal gate oxide(SiO$_2$) of identical thickness. From the measurement results, we find that reoxidized nitrided oxide(ONO) film shows superior dielectric characteristics, leakage current, and breakdown-to-charge(Qbd) performance over the NO film, while maintaining a similar electric field dependence compared to NO layer. Besides, ONO film has strong resistance against variation in temperature.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.2
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• pp.97-101
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• 2003

New Pt/Ti and hi/Ti double-metal structures have been investigated for the application of a diffusion barrier between Cu and Si in deep submicron integrated circuits. Pt/Ti and Ni/Ti were deposited using E-beam evaporator at room temperature. The performance of Pt/Ti and Ni/Ti structures as diffusion barrier against Cu diffusion was examined by charge pumping method, gate leakage current, junction leakage current, and SIMS(secondary ion mass spectroscopy). These evaluation indicated that Pt/Ti(200${\AA}$/100${\AA}$) film is a good barrier against Cu diffusion up to 450$^{\circ}C$.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.1
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• pp.9-15
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• 2021

In multi-string light-emitting diode (LED) driver system, current balancing is crucial because the brightness of LED is directly related to its forward current. This paper presents a novel LED current balancing topology using current-fed Z-source converter. With the proposed structure, currents flowing through two LED strings are automatically balanced owing to the charge-balance condition on capacitors. Operation of the proposed converter is simple and the proposed converter uses only one active switch and one diode. Moreover, low-side gate driving can be used to operate the active switch. To verify the operation of the proposed LED current balancing converter, a prototype is built and tested with different numbers of LEDs.