• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.35-40
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• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.10-17
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• 2012

This paper presents a clock regenerator using two $2^{nd}$ order ${\sum}-{\Delta}$ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different ${\sum}-{\Delta}$ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 ${\mu}m$ CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.

• Korean Journal of Optics and Photonics
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• v.11 no.5
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• pp.330-334
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• 2000

A new pha~e lock loop (PLL) IS proposed and demonstrated fat clock recovery from 40 Gblt/s time-dIvision-multiplexed (TDM) optical pulse tri.lin, The proposed clock lecovery scheme lmproves the Jitter effecl cOlmng from the clock. pulse laser of harmonically-mode locked flber laser The cross-corrdation frequency component between the optical Signa] and an optical clock pulse tram is deteCled as a fonr-wave-mixing (FWM) SIgnal generated in SOA. The lock-in freqnency range of the clod. recovery IS found to be within 10 KHz. 0 KHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1C
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• pp.120-130
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• 2009

In this paper, we propose a receiver structure for frequency synchronization in OFDMA (Orthogonal Frequency Division Multiple Access) system which is considered as 3GPP LTE(Long Term Evolution) downlink. In general, OFDMA frequency synchronization consists of two parts: coarse synchronization and fine synchronization. We consider P-SCH (Primary-Synchronization Channel) and CP (Cyclic Prefix) of OFDMA symbol for coarse synchronization and fine synchronization, respectively. The P-SCH signal has two remarkable disadvantages that it does not have sufficiently many sub-carriers and its differential correlation characteristic is not good due to ZC (Zadoff Chu) sequence-specific property. Hence, conventional frequency synchronization algorithms cannot obtain satisfactory performance gain. In this paper, we propose a modified differential correlation algorithm to improve performance of the coarse frequency synchronization. Also, we introduce an effective PLL (Phase Locked Loop) structure to guarantee stable performance of the fine frequency synchronization. Simulation results verify that the proposed algorithm has superior performance to the conventional algorithms and the 2nd-order PLL is effective to track the fine frequency offset even in high mobility.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.955-958
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• 1999

We designed a phase locked loop (PLL), which is applicable to microprocessor clock generation application. The designed PLL has a new simple phase frequency detector (PFD) which eliminate dead-zone and has a good high frequency characteristic. The lock-in range of the designed PLL is 50 MHz ~ 150 MHz at 3.3v power supply voltage. The design is carried out using a 0.6${\mu}{\textrm}{m}$ triple metal CMOS process. The area of the layout is 0.35mm by 0.42mm with 359 transistors.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.353-356
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• 1999

A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6${\mu}{\textrm}{m}$ n-well CMOS process. The simulation results show a locking time of 2.6$\mu$sec at 1Hz, Lock in range of 100MHz~1㎓, and a power dissipation of 112㎽.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.246-248
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• 2007

This paper presents fast locking PLL(Phase Locked Loop) that can improve a jitter noise characteristics and acquisition process by designing a PFD(Phase Frequency Detector) circuit. The conventional PFD has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. The advanced PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, and it has excellent performances such as 1.75us of locking time and independent duty cycle characteristic. It is fabricated in a 0.018-${\mu}m$ CMOS process, and 1.8v supply voltage, and 25MHz of input oscillator frequency, and 800MHz of output frequency and is simulated by using ADE of Cadence.

• Journal of the Korea Institute of Military Science and Technology
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• v.8 no.4 s.23
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• pp.102-109
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• 2005

In this paper, we propose a new listen-in technique to overcome the problems and the shortcomings which could possibly meet in the previous listen-in methods to deal with the blind signal manually according to operator's decision. In the proposed listen-in method, receiving the signals, classifying the modulation types, and demodulating the signals can be done automatically without operator's intervention. We realize the listen-in technology by developing the high speed frequency tuner, the automatic modulation recognizer, and the signal demodulator. In conclusion, we confirm and show that the developed equipment has a good performance in classifying the modulation type through the computer simulation and the field test.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1948-1951
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• 2002

In this paper, we propose a chip timing recovery algorithm that is robust to frequency offset and time variant fading environments for DS/CDMA. The proposed structure is a modified non-coherent Delay Locked Loop (DLL) that employs a decimator. Analytical expression for the proposed non-coherent DLL S-curve and steady-state timing jitter is derived and confirmed by computer simulation. The results show that the proposed structure can reduce a steady-state timing jitter of the regenerated spreading code replica to frequency offset and time-variant fading in mobile radio channel, especially in very low SNR.