JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Clock Regenerator using Two 2nd Order Sigma-Delta Modulators for Wide Range of Dividing Ratio

  • Received : 2011.07.15
  • Published : 2012.03.31
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Abstract

This paper presents a clock regenerator using two $2^{nd}$ order ${\sum}-{\Delta}$ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different ${\sum}-{\Delta}$ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 ${\mu}m$ CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.

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References

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