Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2007.04a
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- Pages.246-248
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- 2007
Fast locking PLL in moble system using improved PFD
모바일 시스템에 필요한 향상된 위상주파수검출기를 이용한 위상고정루프
- Published : 2007.04.27
Abstract
This paper presents fast locking PLL(Phase Locked Loop) that can improve a jitter noise characteristics and acquisition process by designing a PFD(Phase Frequency Detector) circuit. The conventional PFD has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. The advanced PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, and it has excellent performances such as 1.75us of locking time and independent duty cycle characteristic. It is fabricated in a 0.018-