• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.20-23
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• Design & Manufacturing
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• v.6 no.1
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• pp.95-100
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• 2012

In this study, a novel Cu composite sheet with embedded high electric conduction path was developed as another alternative for the interconnect materials possessing high electrical conductivity as well as high strength. The Cu composite sheet was fabricated by forming Ag conduction paths not within the interior but on the surface of a high strength Cu substrate by damascene electroplating process. As a result, the electrical conductivity increased by 40% thanks to mesh type Ag conduction paths, while the ultimate tensile strength decreased by 20%. The interfacial fracture resistance of Cu composite sheet prepared by damascene electroplating increased by above 50 times compared to Cu composite sheet by conventional electroplating. For feasibility test for practical application, a leadframe for LED module was manufactured by a progressive blanking and piercing processes, and the blanked surface profile was evaluated as a function of the volume fraction of Ag conduction paths. As Ag conduction path became finer, pressing formability improved.

• Journal of Applied Biological Chemistry
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• v.53 no.3
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• pp.184-188
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• 2010

Effect of the plant essential oils on the growth of Malassezia pachydermatis was evaluated and the essential oils of Ocimum basilicum L., Melaleuca alternifolia (Maid. & Bet.) Cheel, and Rosa damascene Mill. were the most active against M. pachydermatis and their activity were high than that of itraconazole at 2 mg/mL. The major constituents of the three oils by GC-MS analysis were linalool (21.83%) and estragole (74.29%) for O. basilicum, a-terpinolene (17.96%) and terpinen-4-01 (45.54%) for M. alternifolia, and a-citronellol (59.98%) and geraniol (27.58%) for R. damascene. Results showed that these selected three oils could be effective toward controlling M. pachydermatis opportunistic infections.

• Transactions on Electrical and Electronic Materials
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• v.6 no.5
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• pp.225-228
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• 2005

In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.103-104
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• 2006

$Pb(Zr,Ti)O_3(PZT)$ is very attractive ferroelectric materials for ferroelectric random access memory (FeRAM) applications because of its high polarization ability and low process temperature. However, Chemical Mechanical Polishing (CMP) pressure and velocity must be carefully adjusted because FeRAM shrinks to high density devices. The contaminations such as slurry residues due to the absence of the exclusive cleaning chemicals are enough to influence on the degradation of PZT thin film capacitors. The surface characteristics of PZT thin film were investigated by the change of process parameters and the cleaning process. Both the low CMP pressure and the cleaning process must be employed, even if the removal rate and the yield were decreased, to reduce the fatigue of PZT thin film capacitors fabricated by damascene process. Like this, fatigue characteristics were partially controlled by the regulation of the CMP process parameters in PZT damascene process. And the exclusive cleaning chemicals for PZT thin films were developed in this work.

• Proceedings of the Korean Vacuum Society Conference
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• 2008.08a
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• pp.147-147
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• 2008

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.111-115
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• 2014

Effect of dynamic electric fields on dielectric breakdown behavior in Cu damascene interconnects was investigated. Among the DC, unipolar, and bipolar pulse conditions, the longest dielectric lifetime is observed under the bipolar condition because backward Cu ion drift occurs when the direction of electric field is changed by 180 degrees and Cu contamination is prohibited as a results. Under the unipolar pulse condition, the dielectric lifetime increases as pulse frequency increases and it exceed the lifetime under DC condition. It suggests that the intrinsic breakdown of dielectrics significantly affect the dielectric breakdown in addition to Cu contamination. As the unipolar pulse width decreases, dielectric bond breakdown is more difficult to occur.

• Journal of the Korean Electrochemical Society
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• v.10 no.2
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• pp.94-103
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• 2007

The transition of interconnection metal from aluminum alloy to copper has been introduced to meet the requirements of high speed, ultra-large scale integration, and high reliability of the semiconductor device. Since copper, which has low electrical resistivity and high resistance to degradation, has different electrical and material characteristics compared to aluminum alloy, new related materials and processes are needed to successfully fabricate the copper interconnection. In this review, some important factors of multilevel copper damascene process have been surveyed such as diffusion barrier, seed layer, organic additives for bottom-up electro/electroless deposition, chemical mechanical polishing, and capping layer to introduce the related issues and recent research trends on them.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.68-73
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• 2006

We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large $V_{TH}$ shifts over 2.5V at 12V/$10{\mu}s$ for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.

• Journal of the Korean Electrochemical Society
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• v.5 no.3
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• pp.153-158
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• 2002

The effects of leveler on the copper trench filling were investigated during damascene plating process. To investigate the trench filling effect with the addition of a leveler, a cross-section images of the electroplated trenches with the width of$0.37{\mu}m,\;and\;0.18{\mu}m$ were observed by field emission scanning electron microscope (FE-SEM). Polyethylene glycol(PEG), 3-mercapto-1-propanesulfonic acid and Janus Green B were used as a carrier, an accelerator and a leveler. $0.37{\mu}m$ trenches were superfilled without voids, but there was voids formation in $0.18{\mu}m$ trenches when the leveler was not added into the electrolyte. On the other hand $0.18{\mu}m$ trenches were superfilled without voids with the addition of the leveler due to the reduction growth rate of copper at protrusions and edges, which yield smooth final deposit surface. The leverer effect becomes more significant as the width of trenches becomes smaller when trenches are filed.