• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.579-582
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• 2008

Three dimensional(3D) Poisson's equation is used to calculate the potential variation in the channel to analyze subthreshold current and short channel effect(SCE). The analytical model has been presented to lessen calculating time and understand the relationship of parameters. The accuracy of this model has been verified by the data from 3D numerical device simulator and variation for dimension and process parameters has been explained. The model has been developed to obtain channel potential of FinFET according to channel doping and to calculate subthreshold current and threshold voltage.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1645-1648
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• 2006

We have developed a CMOS LTPS process, which requires only five photolithographic masks and only one ion doping step. Single TFTs, inverters, ring oscillators and shift registers were fabricated. N- and p-channel devices reached field effect mobilities of $173cm^2/Vs$ and $47cm^2/Vs$, respectively.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.3
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• pp.267-273
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• 1992

An advanced on-resistance model of VDMOS devices in the low voltage regimes is proposed and verified by 2-D device simulations. The model considers the lateral gaussian doping profiles in the channel region and exact current spreading angles in the epitaxial layer for both linear and cellular geometries by employing the conformal mapping, It is found out that the on-resistance of low voltage VDMOS may be overestimated considerably if it is analyzed by the conventional method. The 2-D device simulation results show that the proposed model is valid for the VDMOS devices in the low voltage regimes.

• Journal of Information Display
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• v.8 no.1
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• pp.1-5
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• 2007

We have developed a CMOS LTPS process which requires only five photolithographic masks and only one ion doping step. Drain/Source areas of NMOS TFTs were formed by PECVD deposition of a highly doped precursor layer while PMOS contact areas were defined by ion implantation. Single TFTs, inverters, ring oscillators and shift registers were fabricated. N and p-channel devices reached field effect mobilities of $173cm^2$/Vs and $47cm^2$/Vs, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.51-51
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• 2009

In this paper, we proposed GaN trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, GaN and SiC power devices is next generation power semiconductor devices. We carried out modeling of GaN SIT with 2-D device and process simulator. As a result of modeling, we obtained 340V breakdown voltage. The channel thickness was 3um and the channel doping concentration is 1e17cm-3. And we carried out thermal characteristics, too.

• Journal of Sensor Science and Technology
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• v.26 no.2
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• pp.79-84
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• 2017

The drain current of the SB MOSFET was analytically modeled by an equation composed of thermionic emission and tunneling with consideration of the image force lowering. The depletion region electron concentration was used to model the channel electron concentration for the tunneling current. The Schottky barrier width is dependent on the channel electron concentration. The drain current is changed by the gate oxide thickness and Schottky barrier height, but it is hardly changed by the doping concentration. For a GaN SB MOSFET with ITO source and drain electrodes, the calculated threshold voltage was 3.5 V which was similar to the measured value of 3.75 V and the calculated drain current was 1.2 times higher than the measured.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.12
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• pp.1018-1022
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• 2009

In this paper, we proposed GaN trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, GaN and SiC power devices is next generation power semiconductor devices. We carried out modeling of GaN SIT with 2-D device and process simulator. As a result of modeling, we obtained 340 V breakdown voltage. The channel thickness was 3 urn and the channel doping concentration is $1e17\;cm^{-3}$. And we carried out thermal characteristics, too.

• Journal of Electrical Engineering and Technology
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• v.2 no.4
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• pp.518-524
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• 2007

This paper describes several improved characterizations of the EPIC CCD, which now has modified electrode and channel structures. From a 3-D numerical simulation of the device, its channel doping and potential distributions are then observed for the optimization of the charge transfer. A wavelength-dependence on the device structure is observed in terms of the reflectivity of the incident radiation. The optical properties of ultra-low energy levels, when using an open-electrode structure, are then considered to improve their quantum efficiency.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.5
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• pp.48-53
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• 1998

Poly-Si TFT's could be fabricated on glass substrates by metal induced lateral crystallization (MILC) method at 450.deg. C. Channel area of the poly-Si TFT's was laterally crystallized from source and drain areas, where a thn nickel film was deposited. Dopants activation for the formation of source and drain region could be achieved by thermal annealing at 450.deg. C after the ion mass doping of phosphorus. The field effect mobility of thus formed N-channel poly-Si TFT's was 76cm$^{2}$/Vs, and the on/off current ratio was higher than 7E6.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.