• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.23-34
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• 2005

Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.4
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• pp.44-51
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• 2005

In this paper, a new polishing head with the variable pressure structure was studied to improve the planarization uniformity of the conventional template-metal head. Metal surface waviness and slurry distribution on the pad have been known to affect the polishing uniformity even in the synchronized quill and platen velocities. A polishing head with silicon rubber sheet was used to get a curved pressure distribution. In the experiment, the vertical deflection behavior on the pad was characterized with back pressure in the air chamber. Quill force increased linearly with backpressure. However, backpressure under a quill force made the upward movements of the quill. In the wafer polishing experiments, polishing rate and polishing thickness distribution were severely changed with backpressure. The best uniformity was observed with the standard deviation off.5％ level of average polishing removal 215nm at backpressure 12.1kPa.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.12
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• pp.977-982
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• 2000

Conventional transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area. These consequently have disadvantage for high speed switching performance. In this paper, a lateral structure transistor which has minimized parasitic capacitance by using SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics are designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance is proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed lateral structure transistor is certified through the V$\_$CE/-I$\_$C/ characteristics curve, h$\_$FE/-I$\_$C/ characteristics, and GP-plot. Cutoff Frequency is 13.7㎓.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1998.09a
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• pp.35-40
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• 1998

There have two kinds of defects, planar defects and vertical defects which were called micropipes in SiC bulk crystals grown by a sublimation method. We could decrease these defects by adding a little piece of Si in the SiC powder or using Ta cylinder in the crucible. so were report the dependence of these defects in a wafer on silicon/carbon ratio in this paper. The chemical species sublimed from SiC powder is affected by carbon from the graphite wall of the crucible. It is important to control the chemical species on the substrate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.759-762
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• 2000

Present transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area, consequently have disadvantage for high speed switching performance. In this paper, a horizontal structure transistor which has minimized parasitic capacitance in virtue of SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics were designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance was proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed horizontal structure transistor was certified through the VCE-lC characteristics curve, $h_{FE}$ -IC characteristics, and GP-plot.

• Korean Chemical Engineering Research
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• v.47 no.1
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• pp.1-10
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• 2009

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the enhancement of the semiconductor chip technology due to an increase in RC delay among interconnects. To address this problem, a new technology - "3 dimensional (3D) IC chip stack" - has been emerging. For the integration of the technology, several new key unit processes (e.g., silicon through via, wafer thinning and wafer alignment and bonding) should be developed and much effort is being made to achieve the goal. As a result of such efforts, 4 and 8 chip-stacked DRAM and NAND structures and a system stacking CPU and memory chips vertically were successfully developed. In this article, basic theory, configurations and key unit processes for the 3D IC chip integration, and a current tendency of the technology are explained. Future opportunities and directions are also discussed.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.6
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• pp.1-6
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• 2002

Micro engine that includes Micro scale combustor is fabricated. Design target was focused on the observation of combustion driven actuation in MEMS scale. Combustor design parameters are somewhat less than the size recommended by feasibility test. The engine structure is fabricated by isotropic etching of the photosensitive glass wafers. Electrode is formed by electroplating of the Nickel. Photosensitive glass can be etched isotropically with almost vertical angle. Bonding and assembly of structured photosensitive glass wafer from the engine. Combustor size was determined to be 1mn scale. Piston in cylinder moves by fuel injection and reaction. In firing test, adequate engine operation including ignition, flame propagation and piston motion was observed. Present study warrants further application research on MEMS scale internal combustion power units.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.7
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• pp.831-841
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• 2010

The conventional vertical probe has the thin and long signal path that makes transfer characteristic of probe worse because of the S-shaped structure. So we propose the new vertical probe structure that has branch springs in the S-shaped probe. It makes closed loop when the probe mechanically connects to the electrode on a wafer. We fabricated the proposed vertical probe and measured the transfer characteristic and mechanical properties. Compared to the conventional S-shaped vertical probe, the proposed probe has the overdrive that is 1.2 times larger and the contact force that is 2.5 times larger. And we got the improved transfer characteristic by 1.4 dB in $0{\sim}10$ GHz. Also we developed the simulation model of the probe card by using full-wave simulator and the simulation result is correlated with measurement one. As a result of this simulation model, the cantilever probe and PCB have the worst transfer characteristic in the probe card.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.3 s.36
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• pp.197-205
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• 2005

Development of the packaging is one of the critical issues for commercialization of the RF-MEMS devices. RF MEMS package should be designed to have small size, hermetic protection, good RF performance and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at the temperature below $300{\times}C$ is used. Au-Sn multilayer metallization with a square loop of $70{\mu}m$ in width is performed. The electrical feed-through is achieved by the vertical through-hole via filled with electroplated Cu. The size of the MEMS Package is $1mm\times1mm\times700{\mu}m$. By applying $O_2$ plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface as well as via hole. The shear strength and hermeticity of the package satisfy the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.

• Korean Journal of Optics and Photonics
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• v.24 no.5
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• pp.224-230
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• 2013

Laser Lift-Off (LLO) is a process that removes a GaN or AIN thin layer from a sapphire wafer to manufacture vertical-type LEDs. It consists of a light source, an attenuator, a mask, a projection lens and a beam homogenizer. In this paper, we design an attenuator and a projection lens. We use the 'ZEMAX' optical design software for analysis of depth of focus and for a projection lens design which makes $7{\times}7mm^2$ beam size by projecting a beam on a wafer. Using the 'LightTools' lighting design software, we analyze the size and uniformity of the beam projected by the projection lens on the wafer. The performance analysis found that the size of the square-shaped beam is $6.97{\times}6.96mm^2$, with 91.8 % uniformity and ${\pm}30{\mu}m$ focus depth. In addition, this study performs dielectric coating using the 'Essential Macleod' to increase the transmittance of an attenuator. As a result, for 23 layers of thin films, the transmittance total has 10-96% at angle of incidence $45-60^{\circ}$ in S-polarization.