Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)
- Volume 13 Issue 12
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- Pages.977-982
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- 2000
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- 1226-7945(pISSN)
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- 2288-3258(eISSN)
Characteristics of Lateral Structure Transistor
횡방향 구조 트랜지스터의 특성
Abstract
Conventional transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area. These consequently have disadvantage for high speed switching performance. In this paper, a lateral structure transistor which has minimized parasitic capacitance by using SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics are designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance is proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed lateral structure transistor is certified through the V