• ETRI Journal
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• v.38 no.2
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• pp.244-251
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• 2016

In this paper, we investigate the electrical characteristics of two trench-gate-type super-barrier rectifiers (TSBRs) under different p-body implantation conditions (low and high). Also, design considerations for the TSBRs are discussed in this paper. The TSBRs' electrical properties depend strongly on their respective p-body implantation conditions. In the case of the TSBR with a low p-body implantation condition, it exhibits MOSFET-like properties, such as a low forward voltage ($V_F$) drop, high reverse leakage current, and a low peak reverse recovery current owing to a majority carrier operation. However, in the case of the TSBR with a high p-body implantation condition, it exhibits pn junction diode.like properties, such as a high $V_F$, low reverse leakage current, and high peak reverse recovery current owing to a minority carrier operation. As a result, the TSBR with a low p-body implantation condition is capable of operating as a MOSFET, and the TSBR with a high p-body implantation condition is capable of operating as either a pn junction diode or a MOSFET, but not both at the same time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.2
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• pp.83-87
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• 2020

In this letter, we propose and analyze a new asymmetric structure that can be used for next-generation power semiconductor devices. We compare and analyze the electrical characteristics of the proposed device with respect to those of symmetric devices. The proposed device has a p-emitter on the right side of the cell. The peak electric field is reduced by the shielding effect caused by the p-emitter structure. Consequently, the breakdown voltage is increased. The proposed asymmetric structure has an approximately 100% higher Baliga's figure of merit (~94.22 MW/㎠) than the symmetric structure (~46.93 MW/㎠), and the breakdown voltage of the device increases by approximately 70%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.713-717
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• 2011

This paper was carried out design of 600 V GaN power MOSFET Modeling. We decided trench gate type one for design. we carried out device and process simulation with T-CAD tools. and then, we have extracted optimal device and process parameters for fabrication. we have analysis electrical characteristics after simulations. As results, we obtained 600 V breankdown voltage and $0.4\;m{\Omega}cm^2ultra$ low on resistance. At the same time, we carried out field ring simulation for obtaining high voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.3-6
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• 2004

Power semiconductor devices are being compact, high performance and intelligent thanks to recent remarkable developments of silicon design, process and related packaging technologies. Developments of MOS-gate transistors such as MOSFET and IGBT are dominant thanks to their advantages on high speed operation. In conjunction with package technology, silicon technologies such as trench, charge balance and NPT will support future power semiconductors. In addition, wide band gap material such as SiC and GaN are being studies for next generation power semiconductor devices.

• ETRI Journal
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• v.26 no.1
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• pp.7-13
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• 2004

To improve the characteristics of breakdown voltage and specific on-resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon-on-insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on-resistance. The breakdown voltage and the specific on-resistance of the fabricated device is 352 V and $18.8 m{\Omega}{\cdot}cm^2$ with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on-state is over 200 V and the saturation current at $V_{gs}=5V$ and $V_{ds}$=20V is 16 mA with a gate width of $150{\mu}m$.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.194-200
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• 2012

In this paper, we proposed a SPICE model of high-voltage insulated gate bipolar transistor(IGBT). The proposed model consists of two sub-devices, a MOSFET and a BJT. Basic I-V characteristics and their temperature dependency were realized by adjusting various parameters of the MOSFET and the BJT. To model nonlinear parasitic capacitances such as a reverse-transfer capacitance, multiple junction diodes, ideal voltage and current amplifiers, a voltage-controlled resistor, and passive devices were added in the model. The accuracy of the proposed model was verified by comparing the simulation results with the experimental results of a 1200V trench gate IGBT.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.522-529
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• 2013

In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, $0.18{\mu}m$ 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.

• Journal of IKEEE
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• v.17 no.3
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• pp.360-364
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• 2013

The maximum breakdown voltage's characteristic within the Super Junction MOSFET structure comes from N-Drift and P-Pillar's charge balance. By developing P-Pillar from Planar MOSFET, it was confirmed that the breakdown voltage is improved through charge balance, and by setting the gate voltage at 10V, the characteristic comparisons of Planar MOSFET and Super Junction MOSFET are shown in picture 6. The results show that it had the same breakdown voltage as Planar MOSFET which increased temperature resistance by 87.4% at $.019{\Omega}cm^2$ which shows that by the temperature resistance increasing, the power module's power dissipation improved.

• ETRI Journal
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• v.35 no.3
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• pp.425-430
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• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.