JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Suppression Techniques of Subthreshold Hump Effect for High-Voltage MOSFET

  • Baek, Ki-Ju (Dept. of Semiconductor Eng., Chungbuk National University) ;
  • Na, Kee-Yeol (Dept. of Semiconductor Electronics, Chungbuk Provincial College) ;
  • Park, Jeong-Hyeon (DSD Division, Magnachip Semiconductor) ;
  • Kim, Yeong-Seuk (Dept. of Semiconductor Eng., Chungbuk National University)
  • Received : 2013.04.12
  • Accepted : 2013.06.22
  • Published : 2013.10.31
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Abstract

In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, $0.18{\mu}m$ 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.

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References

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