Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)
- Volume 13 Issue 9
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- Pages.729-734
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- 2000
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- 1226-7945(pISSN)
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- 2288-3258(eISSN)
A study on Improvement of sub 0.1$\mu\textrm{m}$ VLSI CMOS device Ultra Thin Gate Oxide Quality Using Novel STI Structure
STI를 이용한 서브 0.1$\mu\textrm{m}$ VLSI CMOS 소자에서의 초박막게이트산화막의 박막개선에 관한 연구
Abstract
Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1