• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.801-803
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• 2004

The current drive in an MOSFET is limited by the intrinsic channel resistance. All the other parasitic elements in a device structure playa significant role and degrade the device performance. These other resistances need to be less than $10{\%}-20{\%}$ of the channel resistance. To achieve the requirements, we should investigate the methodology of separation and quantification of those resistances. In this paper, we developed the extraction method of resistances using calibrated TCAD simulation. The resistance of the extension region is also partially determined by the formation of a surface accumulation region that forms under the gate in the tail region of the extension profile. This resistance is strongly affected by the abruptness of the extension profile because the steeper the profile is, the shorter this accumulation region will be.

• Journal of IKEEE
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• v.21 no.2
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• pp.150-153
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• 2017

In this paper, a structure of GCNMOS based ESD protection circuit using floating-body technique is proposed. TCAD simulation of Synopsys was used to compare with the conventional GGNMOS and GCNMOS. Compared with the conventional GCNMOS, the proposed ESD protection circuit has lower trigger voltage and faster turn-on-time than conventional circuit because of the added NMOSFET. In the simulation result, the triggering voltage of the proposed ESD protection circuit is 4.86V and the turn-on-time is 1.47ns.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.320-320
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• 2010

최근 결정질 태양전지에 관한 연구 중, 후면 공정에 대한 연구가 중요시 되고 있으며 local back contact 구조는 후면 공정에 관한 연구 중 가장 많은 연구가 이루어지고 있는 분야이다. 특히 local back contact이 형성하는 BSF의 폭, 깊이, 간격은 태양전지의 전기적 특성 및 광학적 특성을 결정짓는 결정적인 요인중 하나이다. 하지만 local back contact 형성을 위한 실험에는 많은 시간과 노력이 필요하며, 많은 시행착오를 겪어야 한다. 따라서 2차원 modeling 함수를 통한 TCAD simulation으로 실험하기 이전에 local back contact구조의 태양전지를 만들고 SR로 각 파장별 양자효율의 변화와 전기적 특성을 분석하여 최적화된 local back contact 구조를 제시할 것이다.

• Journal of IKEEE
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• v.25 no.2
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• pp.371-375
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• 2021

In this paper, a SiC-based LIGBT structure that can be used at high voltage and high temperature is presented. In order to improve the low current characteristic, a dual-emitter symmetrical around the gate is inserted. In order to verify the characteristics of the proposed device, simulation and design were conducted using Sentaurus TCAD simulation, and a comparative study was conducted with a general LIGBT. In addition, splitting was performed by designating a variable for the length of the N-drift region in order to verify the electrical characteristics of the minority carriers. As a result of the simulation it was confirmed that the proposed dual-emitter structure flows a higher current at the same voltage than the conventional LIGBT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.2
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• pp.100-104
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• 2012

Fin-type SONOS (silicon-oxide-nitride-oxide-silicon) flash memory has emerged as novel devices having superior controls over short channel effects(SCE) than the conventional SONOS flash memory devices. However despite these advantages, these also exhibit undesirable characteristics such as corner effect. Usually, the corner effect deteriorates the performance by increasing the leakage current. In this paper, the corner effect of fin-type SONOS flash memory devices is investigate by 3D Process and device simulation and their electrical characteristics are compared to conventional SONOS devices. The corner effect has been observed in fin-type SONOS device. The reason why the memory characteristic in fin-type SONOS flash memory device is not improved, might be due to existing undesirable effect such as corner effect as well as the mutual interference of electric field in the fin-type structure as reported previously.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.195-196
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• 2018

We have investigated electrical and optical characteristics of $H_2Pc$ introduced OLED devices. $H_2Pc$ layer acted on tunnel barrier for incident electrons. we have also observed that energy band of the proposed structure was varied as applied electric field by simulation using TCAD program.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.257-259
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• 2019

We have investigated the electrical coupling in a 3D monolithic NOR gate structure using TCAD simulation. The electrical coupling of 3D monolithic NOR gate can be caused by the transistor located in the upper/lower or diagonal transistors. The drain current of the upper layer NMOSFET is the same when the voltage of PgateB is 0 V and 1 V. It has been confirmed that the electrical coupling in the diagonal direction does not affect the device characteristics.

• Journal of IKEEE
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• v.25 no.2
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• pp.280-284
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• 2021

In this paper, a new ESD protection circuit is proposed to improve the snapback characteristics. The proposed a new structure ESD protection circuit applying the conventional SCR structural change and stack structure. The electrical characteristics of the structure using penta-well and double trigger were analyzed, and the trigger voltage and holding voltage were improved by applying the stack structure. The electron current and total current flow were analyzed through the TCAD simulation. The characteristics of the latch-up immunity and excellent snapback characteristics were confirmed. The electrical characteristics of the proposed ESD protection circuit were analyzed through HBM modeling after forming a structure through TCAD simulator.

• Journal of the Korean Society of Industry Convergence
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• v.5 no.1
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• pp.39-43
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• 2002

In present much CMOS devices used in VLSI circuit and Logic circuit. With increasing a number of device in VLSI, the confidence becomes more serious. This paper describe the mechanism of breakdown on CMOS, especially n-MOS, based on Hydro Dynamic model with device self-heating. Additionally, illustrate the CMOS latch-up characteristics on simplified device structure on this paper.

• Journal of IKEEE
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• v.25 no.4
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• pp.735-740
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• 2021

In this paper, we propose a new ESD protection device with high holding voltage with low current gain of parasitic NPN BJT by improving the structure of the existing LTDDSCR. The electrical characteristics of the proposed protection device were analyzed by HBM simulation using Synopsys' TCAD simulation, and the operation of the added BJT was confirmed by current flow, impact ionization and recombination simulation. In addition, the holding voltage characteristics were optimized with the design variables D1 and D2. As a result of the simulation, it was verified that the new ESD protection device has a higher holding voltage compared to the existing LTDDSCR and has a symmetrical bidirectional characteristic. Therefore, the proposed ESD protection device has high area efficiency when applied to an IC and is expected to improve the reliability of the IC.