• Journal of IKEEE
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• v.18 no.2
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• pp.214-219
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• 2014

In this paper, the usage of tilt-implanted trench Schottky diode(TITSD) based on silicon carbide is proposed. A tilt-implanted trench termination technique modified for SiC is proposed as a method to keep all the potentials confined in the trench insulator when reverse blocking mode is operated. With the side wall doping concentration of $1{\times}10^{19}cm^{-3}$ nitrogen, the termination area of the TITSD is reduced without any sacrifice in breakdown voltage while potential is confined within insulator. When the trench depth is set to 11um and the width is optimized, a breakdown voltage of 2750V is obtained and termination area is 38.7% smaller than that of other devices which use guard rings for the same breakdown voltage. A Sentaurus device simulator is used to analyze the characteristics of the TITSD. The performance of the TITSD is compared to the conventional trench Schottky diode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.447-457
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• 2004

This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit (adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix 0.25${\mu}{\textrm}{m}$, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 10$0^{\circ}C$ and has about 36,639 gates.

• Journal of IKEEE
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• v.17 no.1
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• pp.77-82
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• 2013

In this paper, dc-dc buck converter controled by the peak current-mode pulse-width-modulation (PWM) presented. Based on the small-signal model, we propose the novel methods of the power stage and the systematic stability designs. To improve the reliability and performance, over-temperature and over-current protection circuits have been designed in the dc-dc converter systems. To prevent electrostatic An electrostatic discharge (ESD) protection circuit is proposed. The proposed dc-dc converter circuit exhibits low triggering voltage by using the gate-substrate biasing techniques. Throughout the circuit simulation, it confirms that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS (8.2V). The circuit simulation is performed by Mathlab and HSPICE programs utilizing the 0.35um BCD (Bipolar-CMOS-DMOS) process parameters.

• Journal of IKEEE
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• v.20 no.3
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• pp.295-298
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• 2016

In this paper, we analysed the properties of the conventional ESD protection devices such as SCR, MVSCR, LVTSCR. The electrical characteristics and the turn-on time properties are simulated by Synopsys T-CAD simulator. As the results, the devices have the holding voltages between 2V and 3V, and the trigger voltage of about 20V with SCR, of about 12V with MVSCR, of about 9V with LVTSCR. The results of the simulation for the turn-on time properties are 2.8ns of SCR, 2.2ns of MVSCR, 2.0ns of LVTSCR. Thus, we prove that LVTSCR has the shortest turn-on time. However, the second breakdown currents(It2) of the devices are 7.7A of SCR, 5.5A of MVSCR, 4A of LVTSCR. This different properties have to be adapted by the operation voltages for I/O Clamps.

• Journal of IKEEE
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• v.21 no.1
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• pp.7-12
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• 2017

This paper proposed the ESD protection circuit for the high-voltage applications with latch-up immunity and high area efficiency. The proposed circuit has high holding voltage compared to the conventional SCR by inserting the floating regions and applying the segmentation layout. It has the area efficiency is more higher due to the segmentation layout. The proposed circuit has the higher holding voltage of the 21.67V than the 3.39V of the conventional SCR. The electrical characteristics of the proposed circuit was investigated by TCAD simulator, and was proved through the fabrication by using the 0.18 BCD process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.360-367
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• 2006

In this paper, we designed a digital codec of an RFID tag for EPC global generation 2 class 1. There are a large number of studies on RRD standard and anti-collision algorithm but few studies on the design of digital parts of the RFID tag itself. For this reason, we studied and designed the digital codec hardware for EPC global generation 2 class 1 tag. The purpose of this paper is not to improve former studies but to present the hardware architecture, an estimation of hardware size and power consumption of digital part of the RFID tag. Results are synthesized using Synopsys with a 0.35um standard cell library. The hardware size is estimated to be 111640 equivalent inverters and dynamic power is estimated to be 10.4uW. It can be improved through full-custom design, but we designed using a standard cell library because it is faster and more efficient in the verification and the estimation of the design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.791-797
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• 2001

In this paper, high-speed ,large-capacity ATM switching-chip is developed by MCM technology. MCM technology is suited for light-weight portable communications, mobile computing, high-frequency applications. For test of the developed MCM switching-chips, the simulating model is made by VHDL code of previously developed chip and input-output values of modeling pattern are obtained through the simulation. After the pattern values in chip-test machine are inserted , their results are compared with the simulation results. The design in this paper is simulated by synopsys design tool using SUN workstation and functions of chip is measured by TRILLIUM machine. Simulated and measured results have been compared, showing close agreement. Last, the MCM technique presented in this paper will provide useful insight into future designs.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.115-124
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• 2015

In this paper, the method which improves the performance of a serial decimal multiplier, and the method which operates multiple-digit simultaneously are proposed. The proposed serial decimal multiplier reduces the delay by removing encoding module that generates 2X, 4X multiples, and by generating partial product using shift operation. Also, this multiplier reduces the number of operations using multiple-digit operation. In order to estimate the performance of the proposed multiplier, we synthesized the proposed multiplier with design compiler with SMIC 110nm CMOS library. Synthesis results show that the area of the proposed serial decimal multiplier is increased by 4%, but the delay is reduced by 5% compared to existing serial decimal multiplier. In addition, the trade off between area and latency with respect to the number of concurrent operations in the proposed multiple-digit multiplier is confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.201-208
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• 2012

In this paper, the hardware design of rate control for real-time video encoded is proposed. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. For high speed and low computational prediction, the MAD is predicted based on the coded basic unit, using spacial and temporal correlation in sequences. The rate control is designed with the hardware for fast QP decision. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. In addition, the rate control is designed with the hardware for fast QP decision. The execution cycle and gate count of the proposed architecture were reduced about 65% and 85% respectively compared with those of previous architecture. The proposed RC was implemented using Verilog HDL and synthesized with UMC $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count of the architecture is about 19.1k with 108MHz clock frequency.