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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A Design of Peak Current-mode DC-DC Buck Converter with ESD Protection Devices

ESD 보호 소자를 탑재한 Peak Current-mode DC-DC Buck Converter

  • Park, Jun-Soo (Dept. of Electronics and Electrical Engineering, Dankook University) ;
  • Song, Bo-Bae (Dept. of Electronics and Electrical Engineering, Dankook University) ;
  • Yoo, Dae-Yeol (Dept. of Electronics and Electrical Engineering, Dankook University) ;
  • Lee, Joo-Young (Dept. of Electronics Engineering, Seokyeong University) ;
  • Koo, Yong-Seo (Dept. of Electronics and Electrical Engineering, Dankook University)
  • Received : 2013.03.12
  • Accepted : 2013.03.20
  • Published : 2013.03.30
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Abstract

In this paper, dc-dc buck converter controled by the peak current-mode pulse-width-modulation (PWM) presented. Based on the small-signal model, we propose the novel methods of the power stage and the systematic stability designs. To improve the reliability and performance, over-temperature and over-current protection circuits have been designed in the dc-dc converter systems. To prevent electrostatic An electrostatic discharge (ESD) protection circuit is proposed. The proposed dc-dc converter circuit exhibits low triggering voltage by using the gate-substrate biasing techniques. Throughout the circuit simulation, it confirms that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS (8.2V). The circuit simulation is performed by Mathlab and HSPICE programs utilizing the 0.35um BCD (Bipolar-CMOS-DMOS) process parameters.

본 논문에서는 인덕터의 흐르는 전류를 감지하여 출력 전압을 일정하게 유지시키는 Peak Current-mode 방식의 DC-DC Buck Converter를 제안하고, 소신호 모델링에 기초하여 Power Stage 설계 방법과 시스템의 안정도를 설계하는 방법을 제안한다. 또한, dc-dc 컨버터의 신뢰성과 성능을 향상시키기 위해 보호회로를 추가하였다. 그리고 정전기 방지를 위하여 ESD 보호회로를 제안하였다. 제안된 보호회로는 게이트-기판 바이어싱 기술을 이용하여 낮은 트리거 전압을 구현하였다. 시뮬레이션 결과는 일반적인 ggNMOS의 트리거 전압(8.2V) 에 비해 고안된 소자의 트리거 전압은 4.1V 으로 더 낮은 트리거 전압 특성을 나타냈다. 본 논문에서 제안하는 회로의 시뮬레이션은 0.35um BCB 공정 파라미터를 이용하였고, Mathworks 사의 Mathlab과 Synopsys 사의 HSPICE 프로그램을 사용하여 검증하였다.

Keywords

References

  1. CHEN Xiao-fei, "System modeling and stability design for peak current-mode buck power converter" The IEEE INDIN, DDC, Daejeon, Korea, pp. 933-938. July 13-16, 2008.
  2. Hiroki SAKURAI, "Analysis and Design of a Current-Mode PWM Buck Converter Adopting the Output-Voltage Independent Second-Order Slope Compensation Scheme" IEICE TRANS. Fundamentals, Vol. E88-A, No.2, pp. 490-497, February, 2005. https://doi.org/10.1093/ietfec/E88-A.2.490
  3. H. Gossner, "ESD protection for the deep sub-micron regime - A challenge for design methodology", Proc. International Conference. VLSI Design, pp. 809-818, 2004.
  4. M. D. Ker, T. Y. Chen, C. Y. Wu, "ESD protection design in a 0.18${\mu}m$ salicide CMOS technology by using substrate-triggered technique", IEEE Int Symp Cir Sys, pp. 754-757, 2001.

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  2. 빠른 응답특성을 갖는 DC/DC 컨버터 하이브리드 전류 모드 제어기 vol.24, pp.2, 2013, https://doi.org/10.6113/tkpe.2019.24.2.134