• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.1
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• pp.10-18
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• 2000

This paper proposes a fuzzy logic cross-coupled controller using a new contouring modeling for a two-axis servo system. The general decoupled control approach may result in degraded contouring performance due to such factors as mismatch of axial dynamics and axial loop gains. In practice, such systems contain many uncertainties. The cross-coupled controller utilizes all axis position error information simultaneously to produce accurate contours. However, the conventional cross-coupled controllers cannot overcome friction, backlash, and parameter variations. Also since, it is difficult to obtain an accurate mathematical model of multi-axis system, here we investigate a fuzzy logic cross-coupled controller of servo system. In addition, new contouring error vector computation method is presented. The experimental results are presented to illustrate the performance of the proposed algorithm.

• Journal of Microbiology
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• v.38 no.3
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• pp.160-168
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• 2000

A-factor I a microbial hormone that can positively control cell differentiation leading to spore formation and secondary metabolite formation in Streptomyces griseus. to identify a protease that is deeply involved in the morphological and physiological differentiation of Streptomyces, the proteases produced by Streptomyces griseus IFO 13350 and its A-factor deficient mutant strain, Streptomyces griseus HH1, as well as Streptomyces griseus HH1 transformed with the afsA gene were sturdied. In general Streptomyces griseus showed a higher degree of cell growth and protease activity in proportion to its ability to produce a higher amount of A-factor. In particular, the specific activity of the trypsin of Streptomyces griseus IFO 13350 was greatly enhanced more than twice compared with that of Streptomyces griseus HH1 in the later stage of growth. The specific activity of the metalloprotease of Streptomyces griseus HH1 was greatly enhanced more than twice compared with that of Streptomyces griseus IFO 13350, and this observation was reversed in the presence of thiostreptione, However, Streptomyces griseus HH1 transformed with the afsA gene showed a significantly decreased level of trypsin and metalloprotease activity compared with that of the HH1 strain. There was no significant difference between Streptomyces griseus IFO 13350 and HH1 strain in their chymotrypsin and thiol protease activity, yet the level of leu-amionpeptidase activity was 2 times higher in Streptomyces griseus HH1 than in strain IFO 13350 . Streptomyces griseus HH1 harboring afsA showed a similar level of enzyme activity , however, all the three protease activities sharply increased and the thiol protease activity was critically increased at the end of the fermentation. When a serine protease inhibitor, pefabloc SC, and metalloprotease inhibitor, EDTA, were applied to strain IFO 13350 to examine the in vivo effects of the protease inhibitors on the morpholofical differentiation, the formation of aerial meycelium and spores was delayed by two or three days.

• Journal of Power System Engineering
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• v.21 no.6
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• pp.68-78
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• 2017

Major countries have tighten their NOx regulation of diesel passenger cars. In the case of the EU, the regulation has been toughen up to 6.25 times since 2000. Despite the regulation the NOx concentration of the ambient has not been reduced proportionally. Futhermore, some manufacturers were disclosed using a defeat device for meeting the regulation illegally. As these issues, to reduce NOx emission practically, Korea and the EU introduced the real-world driving emission(RDE) regulation and the test method that will be applied after 2017. Also, the US has used the test equipment(PEMS) to detect a defeat device. In this paper, for the regulation to make a soft landing in Korea, 4 diesel passenger cars which met Euro 6a~6b regulation and were equipped with LNT/SCR were tested at a chassis dynamometer with environmental chamber applying the off-cycles(FTP, US06, SC03, HWFET and CADC) and several ambient condition(-7 and $14^{\circ}C$) as well as certification mode(NEDC, WLTC@ $23^{\circ}C$). The result of the test showed that the ambient temp. and the engine load as a test mode impacted the NOx emission of the cars while the vehicles with SCR emitted NOx lower than with LNT. Additionally, to propose an effective RDE test method, the above result was compared with the results of the other papers which tested RDE using the same cars.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.29-36
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• 2000

The principle and design of two-stage CMOS operational amplifier with rail-to-rail input and class-AB output stage is presented. The rail-to-rail input stage shows almost constant transconductance independent of the common mode input voltage range in global transistor operation region. This new technique does not make use of accurate current-voltage relationship of MOS transistors. Hence it was achieved by using simple linear relationship of currents. The simulated transconductance variation using SPICE is less the 4.3%. The proposed global two-stage opamp can operate both in strong inversion and in weak inversion. Class AB output stage proposed also has a full output voltage swing and a well-defined quiescent current that does not depend on power supply voltage. Since feedback class- AB control is used, it is expected that this output stage can be operating in extremely low voltage. The variation of DC-gain and unity-gain frequency is each 4.2% and 12%, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.37-42
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• 2000

In this paper, The high-speed, low-Power analog-to-digital conversion structure is proposed using the pipelined comparator away for high-speed conversion rate and the successive- approximation structure for low-power consumption. This structure is the successive-approximation structure using pipelined comparator array to change the reference voltage during the holding time. An 8-bit 10MS/s analog-to-digital converter is designed using 0.8${\mu}{\textrm}{m}$ CMOS technology. The INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41㏈ at a sampling rate of 10MHz with 100KHz sine input signal. The Power consumption is 4.14㎽ at 10MS/s.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.43-49
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• 2000

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications ate presented. The circuit approach is based on the characteristic of the LV(Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by 0.6${\mu}{\textrm}{m}$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to $\pm$0.5V with a linearity error of less than 1%. The measured -3㏈ bandwidth is 290MHz and the power dissipation is 373㎼. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.50-59
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• 2000

Stereo vision is a technique extracting depth information from stereo images, which are two images that view an object or a scene from different locations. The most important procedure in stereo vision, which is called stereo matching, is to find the same points in stereo images. It is difficult to match stereo images in real time because stereo matching requires heavy calculation. In this Paper we design a digital VLSI to Process stereo matching in real time, which we call stereo image match processor (SIMP). For implementation of real time stereo matching, sliding memory and minimum selection tree are presented. SIMP is designed with pipeline architecture and parallel processing. SIMP takes 64 gray level 64$\times$64 stereo images and yields 8 level 64 $\times$64 disparity map by 3 bit disparity and 12 bit address outputs. SIMP can process stereo images with process speed of 240 frames/sec.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.35-41
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• 2000

This paper describes a merged-capacitor switching (MCS) technique to improve the signal Processing speed and resolution of CMOS analog-to-digital converters (ADCs). The proposed MCS technique improves a sampling rate by reducing the number of capacitors used in conventional pipelined ADCs. The ADC capacitor mismatch can be minimized without additional power consumption, die area, and the loss of sampling rate, when the size of each unit capacitor is increased as much as the number of capacitors reduced by the MCS technique. It is verified that the ADC resolution based on the proposed MCS technique is extended further by employing a conventional commutated feedback-capacitor switching (CFCS) technique.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.42-49
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• 2000

In this paper, we propose the parallel ternary logic circuit design algorithm to DCG Property with 2$^n$ nodes. To increase circuit integration, one of the promising approaches is the use of multiple-valued logic(MVL). It can be useful methods for the realization of compact integrated circuit, the improvement of high velocity signal processing using parallel signal transmission and the circuit design algorithm to optimize and satisfy the circuit property. It is all useful method to implement high density integrated circuit. In this paper, we introduce matrix equation to satisfy given DCG with 2$^n$ nodes, and propose the parallel ternary logic circuit design process to circuit design algorithm. Also, we propose code assignment algorithm to satisfy for the given DCG property. According to the simulation result of proposed circuit design algorithm, it have the following advantage ； reduction of the circuit signal lines, computation time and costs.