Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Merged-Capacitor Switching Technique for Sampling-Rate and Resolution Improvement of CMOS ADCs)

CMOS A/D 변환기의 샘플링 속도 및 해상도 향상을 위한 병합 캐패시터 스위칭 기법

  • Published : 2000.11.01
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Abstract

This paper describes a merged-capacitor switching (MCS) technique to improve the signal Processing speed and resolution of CMOS analog-to-digital converters (ADCs). The proposed MCS technique improves a sampling rate by reducing the number of capacitors used in conventional pipelined ADCs. The ADC capacitor mismatch can be minimized without additional power consumption, die area, and the loss of sampling rate, when the size of each unit capacitor is increased as much as the number of capacitors reduced by the MCS technique. It is verified that the ADC resolution based on the proposed MCS technique is extended further by employing a conventional commutated feedback-capacitor switching (CFCS) technique.

본 논문에서는 전형적인 파이프라인 CMOS A/D 변환기(ADC)의 신호 처리 속도와 해상도를 향상시키기 위해 병합 캐패시터 스위칭(merged-capacitor switching MCS)기법을 제안한다. 제안하는 MCS 기법은 기존의 ADC에 사용되는 multiplying digital-to-analog converter(MDAC)의 캐패시터 수를 50%로 줄임으로써, 부하 캐패시터의 감소로 인해 샘플링 속도를 크게 향상시킬 수 있다. 또한, MCS 기법에서 줄어든 캐패시터 수에 해당하는 크기만큼 각 캐패시터 크기를 2배 증가시킬 경우, 전력 소모 및 샘플링 속도의 감소없이 캐패시터 부정합을 최소화하며, 전체 ADC의 해상도 향상이 가능하다. 제안하는 MCS 기법을 적용한 ADC에 기존의 궤환 캐패시터 스위칭(commutated feedback-capacitor switching : CFCS) 기법을 일부 적용할 경우, 12 비트 이상의 더 높은 해상도를 얻을 수 있고, 응용의 다양화를 고려할 수 있다.

Keywords

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