Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Study on the Parallel Ternary Logic Circuit Design to DCG Property with 2n nodes

$2^n$개의 노드를 갖는 DCG 특성에 대한 병렬3치 논리회로 설계에 관한 연구

  • Published : 2000.11.01
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Abstract

In this paper, we propose the parallel ternary logic circuit design algorithm to DCG Property with 2$^n$ nodes. To increase circuit integration, one of the promising approaches is the use of multiple-valued logic(MVL). It can be useful methods for the realization of compact integrated circuit, the improvement of high velocity signal processing using parallel signal transmission and the circuit design algorithm to optimize and satisfy the circuit property. It is all useful method to implement high density integrated circuit. In this paper, we introduce matrix equation to satisfy given DCG with 2$^n$ nodes, and propose the parallel ternary logic circuit design process to circuit design algorithm. Also, we propose code assignment algorithm to satisfy for the given DCG property. According to the simulation result of proposed circuit design algorithm, it have the following advantage ； reduction of the circuit signal lines, computation time and costs.

본 논문에서는 2ⁿ개의 노드를 갖는 DCG 특성에 대한 병렬 3치 논리회로를 설계하는 알고리즘을 제안하였다. 회로의 집적도를 높이기 위한 다양한 연구분야 중 전송선의 신호레벨을 증가시켜줌으로써 회로내의 배선밀도를 낮출 수 있으며 병렬신호전송을 통한 신호처리의 고속화, 회로의 특성을 만족시키며 최적화할 수 있는 회로설계알고리즘은 모두 고밀도 집적회로를 구현하기 위한 유용한 수단이 될 수 있다. 본 논문에서는 특히, 노드들의 개수가 2ⁿ개로 주어진 DCG에 대하여 그 특성을 행렬방정식으로 도출해내고 이를 통해 최적화 된 병렬3치 논리회로를 설계하는 과정을 정리하여 알고리즘으로 제안하였다. 또한, 설계된 회로의 동작특성을 만족하도록 DCG의 각 노드들의 코드를 할당하는 알고리즘도 제안하였다. 본 논문에서 제안된 알고리즘에 의해 회로결선의 감소와 처리속도 향상, 비용절감 측면에서 유용하다 할 수 있다.

Keywords

References

  1. M. Karreyarna, 'Toward The Age of BeyondBinary Electronics and Systems', IEEE Proc. 20th Int. Sym-posium on Multiple-Valued Logic, pp. 162-166, May. 1990 https://doi.org/10.1109/ISMVL.1990.122613
  2. K. C. Smith and P. G. Gulak, 'Prospects for multiple-valued intergrated circuits,' Special issue on Multiple Valued intergrated Circuits IEICE TRANS. ELECIRON., Vol. E76-C, No. 3, pp. 372-382, Mar. 1993
  3. T. Hanyu, M. Nakajima and T, Higuchi, 'Prospects of multiple-valued VLSI processors,' Special issue on Multiple-Valued intergrated Circuits IEICE TRANS. ELECTRON., Vol. E76-C, No.3, pp. 383-392, Mar. 1993
  4. S. Tamaki, M. Kameyama, and T, Higuchi, 'Code Assignment Algorithm for Highly Parallel Multiple- Valued Combinational Circuits', IEEE Proc. 22th Int. Symposium on Multiple-Valued Logic. pp. 382-388, May. 1992 https://doi.org/10.1109/ISMVL.1992.186820
  5. M. Nakajima and M. Karreyama, 'Design of Multiple-valued Linear Digital Circuits for Highly Parallel Unary Operations', IEEE Proc. 23th Int. Symposium on Multiple-Valued Logic, pp. 283-288, May. 1993 https://doi.org/10.1109/ISMVL.1993.289546
  6. M. Nakajima and M. Kameyama, 'Design of Highly Parallel Linear Digital System for ULSI Processors', IEICE Trans, Vol. E76-C, No. 7, pp. 1119-1125, Jul. 1993
  7. M. Nakajima and M. Kameyama, 'Design of Multiple-valued Linear Digital Circuits for Highly Parallel k-ary Operations', IEEE Proc. 24th Int. Symposium on Multiple-Valued Logic, pp. 223-230, May. 1994 https://doi.org/10.1109/ISMVL.1994.302197
  8. M. Ryu and M. Kameyama, 'Design of a Highly Parallel Multiple-valued Linear Digital Circuits for k-ary Operations Based on Extended Representation Matrices', IEEE Proc. 25th Int. Symposium on Multiple-Valued Logic, pp. 20-25, May. 1995 https://doi.org/10.1109/ISMVL.1995.513505
  9. M. Nakajima and M. Kameyama, 'Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy', IEEE Proc. 26th Int. Symposium on Multiple-Valued Logic, pp. 104-109, May. 1996 https://doi.org/10.1109/ISMVL.1996.508344
  10. R. J. Wilson and J. J. Watkins, GRAPH An Introductory Approach, John Wiley & Sons, Inc. 1990
  11. Douglas B. West, Introduction to Graph Theory, Prentice Hall, Inc. 1996
  12. E. Artin, Galois Theory, NAPCO Graphic arts, Inc., Wilconsin. 1971
  13. Robert J. McEIiece, Finite Fields for Computer Scientists and Engineers, Kluwer Academic Publisher, 1978
  14. A. Gill, Linear Sequential Circuits, McGraw-Hill Book Co., Newyork, 1966