• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1609-1611
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• 1996

The on-resistance characteristics of the RESURF LDMOS and VDMOS are compared. The on-resistance vs. breakdown characteristics of the RESURF LDMOS is analytically investigated. The on-resistance of RESVRF LDMOS is as almost same as that of VDMOS.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 C
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• pp.1621-1623
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• 1997

The breakdown voltage of SOI RESURF (REduce SURface Field) diode using a SIPOS (Semi Insulating POlycrystalline Silicon) layer is verified in terms of n-drift layer length and surface oxide thickness by device simulator MEDICI, and compared with conventional SOI RESURF diode. Increasing the n-drift layer length, the breakdown voltage of SOI RESURF diode using the SIPOS layer have increased and saturated at $8{\mu}m$. And it has decreased with increasing the surface oxide thickness.

• 전자공학회논문지A
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• 제33A권7호
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• pp.176-184
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• 1996

To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 추계학술대회 논문집 전기물성,응용부문
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• pp.57-59
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• 2005

전력용 IC에서 높은 항복전압의 구현을 위해서 RESURF구조가 많이 사용되고 있다. 하지만 하나의 칩 위에서 다양한 항복전압을 가지는 소자를 구현하기 위해서는 에피층의 농도가 각각 달라져야하는데 이는 공정상의 복잡함과 비용의 문제를 수반하게 된다. 이런 문제점에 따라 본 연구에서는 전력용 IC에서 항복전압이 다른 다수의 LDMOST를 추가 공정없이 에피 영역의 길이를 조절하여 구현할 수 있음을 해석적인 방볍과 2차원 소자 시뮬레이터를 이용하여 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.361-364
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• 2004

Surface doped SOI RESURF LDMOSFET with recessed source region is proposed to improve the on- and off-state characteristics. Surface region of the proposed LDMOS structure is doped like step. The characteristics of the proposed LDMOS is verified by two-dimensional process simulator ATHENA and device simulator ATLAS[1]. The numerically calculated on-resistance($R_{ON}$) of the proposed LDMOS is $10.36\Omega-cm$ and breakdown voltage is 205V when $L_{dr}=7{\mu}m$ with step doped surface.

• 한국전기전자재료학회논문지
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• 제19권1호
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• pp.23-28
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• 2006

In this paper, breakdown voltage and on-resistance characteristics of the surface doped SOI RESURF LDMOSFET were investigated as a function of surface doping depth. In order to verify the variation of characteristics, two-dimensional device simulation was carried out. Breakdown voltage of the proposed structure is varied from $73 {\~}138V$ while surface doping depth varied from $0.5{\~}2.0{\mu}m$. And on-resistance is decreased from $0.18{\~}0.143{\Omega}/cm^2$ while surface doping depth increased from $0.5 {\~}2.0{\mu}m$. Maximum breakdown voltage of the proposed structure is 138 V at $1.5{\mu}m$ depth of surface doping, yielding $22.1\%$ of improvement of breakdown voltage in comparison with that of the conventional SOI RESURF LDMOSFET with same epi-layer concentration. On-resistance characteristic is also improved about $21.7\%$.

• 한국전기전자재료학회논문지
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• 제19권9호
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• pp.813-817
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• 2006

In this paper, we analyzed the breakdown voltage and on-resistance of the multi-RESURF SOI LDMOSFET as a function of epi-layer concentration. P-/n-epi layer thickness and doping concentration of the proposed structure are varied from $2{\sim}5{\mu}m\;and\;1\{times}10^{15}/cm^{3}^{\sim}9\{times}10^{15}/cm^{3}$ to find optimum breakdown voltage and on-resistance of the proposed structure. The maximum breakdown voltage of the proposed structure is $224\;V\;at\;R_{on}=0.2{\Omega}-mon^{2}\;with\;P_{epi}=3\{times}10^{15}/cm^{3},\;N_{epi}=7\{times}10^{15}/cm^{3}\;and\;L_{epi}=10{\mu}m$. Characteristics of the device are verified by two-dimensional process simulator ATHENA and device simulator ATLAS.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.110-111
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• 2006

이중 에피층을 가지는 SOI (Silicon-On-Insulator) RESURF(REduced SURface Field) LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자의 에피층 두께에 따른 항복전압 특성을 분석하였다. 이중 에 피층 구조를 가지는 SOI RESURF LIGBT 소자는 전하보상효과를 얻기 위해 기존 LIGBT 소자의 n 에피로 된 영역을 n/p 에피층의 이중 구조로 변경한 소자로 n/p 에피층 영역내의 전하간 상호작용에 의해 에피 영역 전체가 공핍됨으로써 높은 에피 영역농도에서도 높은 항복전압을 얻을 수 있는 소자이다. 본 논문에서는 LIGBT 에피층의 전체 두께와 농도를 고정한 상태에서 n/p 에피층의 두께가 변하는 경우에 항복전압 특성의 변화에 대해 simulation을 통해 분석하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1606-1608
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• 1996

An the SOI RESURF LDMOS with a taper oxide on the drain is proposed and verified by the device simulator, MEDICI. Simulation results on the proposed LDMOS exhibits the increase in the breakdown voltage by 12 % and reduction in the drift region length by 25 %.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 C
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• pp.1578-1580
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• 2002

The breakdown and on-state characteristics of the multi-RESURF SOI LDMOSFET is presented. P-/n-epi layer thickness and doping concentration is varied from $2{\mu}m{\sim}5{\mu}m$ and $1{\times}10^{15}/cm^3{\sim}9{\times}10^{15}/cm^3$ to obtain optimum breakdown voltage and on-resistance. The breakdown and on-state characteristics of the device is verified by two-dimensional process simulator ATHENA and device simulator ATLAS.